Static Timing Analysis

Project : asp_eval1
Build Time : 08/31/16 21:40:00
Device : CY8C5868AXI-LP035
Temperature : -40C - 85/125C
VDDA : 5.00
VDDABUF : 5.00
VDDD : 5.00
VDDIO0 : 5.00
VDDIO1 : 5.00
VDDIO2 : 5.00
VDDIO3 : 5.00
VUSB : 5.00
Voltage : 5.0
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+ Timing Violation Section
No Timing Violations
+ Clock Summary Section
Clock Domain Nominal Frequency Required Frequency Maximum Frequency Violation
CyBUS_CLK(fixed-function) CyBUS_CLK(fixed-function) 24.000 MHz 24.000 MHz N/A
CyILO CyILO 1.000 kHz 1.000 kHz N/A
CyIMO CyIMO 3.000 MHz 3.000 MHz N/A
CyMASTER_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz N/A
CyBUS_CLK CyMASTER_CLK 24.000 MHz 24.000 MHz 55.457 MHz
Clock_2 CyMASTER_CLK 12.000 MHz 12.000 MHz 88.921 MHz
Clock_3 CyMASTER_CLK 12.000 MHz 12.000 MHz 61.927 MHz
UART_1_IntClock CyMASTER_CLK 923.077 kHz 923.077 kHz 55.276 MHz
UART_2_IntClock CyMASTER_CLK 923.077 kHz 923.077 kHz 45.323 MHz
UART_4_IntClock CyMASTER_CLK 923.077 kHz 923.077 kHz 54.416 MHz
UART_3_IntClock CyMASTER_CLK 461.538 kHz 461.538 kHz 50.201 MHz
CyPLL_OUT CyPLL_OUT 24.000 MHz 24.000 MHz N/A
CyXTAL CyXTAL 24.000 MHz 24.000 MHz N/A
+ Register to Register Section
+ Setup Subsection
Path Delay Requirement : 83.3333ns(12 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_AUDIO:PWMUDB:genblk8:stsreg\/status_2 88.921 MHz 11.246 72.087
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell13 U(1,1) 1 \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\ \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/clock \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
Route 1 \PWM_AUDIO:PWMUDB:tc_i\ \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_AUDIO:PWMUDB:status_2\/main_1 2.791
macrocell41 U(1,1) 1 \PWM_AUDIO:PWMUDB:status_2\ \PWM_AUDIO:PWMUDB:status_2\/main_1 \PWM_AUDIO:PWMUDB:status_2\/q 3.350
Route 1 \PWM_AUDIO:PWMUDB:status_2\ \PWM_AUDIO:PWMUDB:status_2\/q \PWM_AUDIO:PWMUDB:genblk8:stsreg\/status_2 2.315
statusicell9 U(1,1) 1 \PWM_AUDIO:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 89.742 MHz 11.143 72.190
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell13 U(1,1) 1 \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\ \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/clock \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/z0_comb 2.290
datapathcell13 U(1,1) 1 \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\ \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/z0_comb \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cs_addr_2 2.793
datapathcell13 U(1,1) 1 \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM_AUDIO:PWMUDB:runmode_enable\/q \PWM_AUDIO:PWMUDB:genblk8:stsreg\/status_2 93.580 MHz 10.686 72.647
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell115 U(1,1) 1 \PWM_AUDIO:PWMUDB:runmode_enable\ \PWM_AUDIO:PWMUDB:runmode_enable\/clock_0 \PWM_AUDIO:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_AUDIO:PWMUDB:runmode_enable\ \PWM_AUDIO:PWMUDB:runmode_enable\/q \PWM_AUDIO:PWMUDB:status_2\/main_0 3.271
macrocell41 U(1,1) 1 \PWM_AUDIO:PWMUDB:status_2\ \PWM_AUDIO:PWMUDB:status_2\/main_0 \PWM_AUDIO:PWMUDB:status_2\/q 3.350
Route 1 \PWM_AUDIO:PWMUDB:status_2\ \PWM_AUDIO:PWMUDB:status_2\/q \PWM_AUDIO:PWMUDB:genblk8:stsreg\/status_2 2.315
statusicell9 U(1,1) 1 \PWM_AUDIO:PWMUDB:genblk8:stsreg\ SETUP 0.500
Clock Skew 0.000
\PWM_AUDIO:PWMUDB:runmode_enable\/q \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 94.455 MHz 10.587 72.746
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell115 U(1,1) 1 \PWM_AUDIO:PWMUDB:runmode_enable\ \PWM_AUDIO:PWMUDB:runmode_enable\/clock_0 \PWM_AUDIO:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_AUDIO:PWMUDB:runmode_enable\ \PWM_AUDIO:PWMUDB:runmode_enable\/q \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.277
datapathcell13 U(1,1) 1 \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\ SETUP 6.060
Clock Skew 0.000
\PWM_AUDIO:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_AUDIO:PWMUDB:runmode_enable\/main_0 109.385 MHz 9.142 74.191
Type Location Fanout Instance/Net Source Dest Delay (ns)
controlcell1 U(1,4) 1 \PWM_AUDIO:PWMUDB:genblk1:ctrlreg\ \PWM_AUDIO:PWMUDB:genblk1:ctrlreg\/clock \PWM_AUDIO:PWMUDB:genblk1:ctrlreg\/control_7 1.210
Route 1 \PWM_AUDIO:PWMUDB:control_7\ \PWM_AUDIO:PWMUDB:genblk1:ctrlreg\/control_7 \PWM_AUDIO:PWMUDB:runmode_enable\/main_0 4.422
macrocell115 U(1,1) 1 \PWM_AUDIO:PWMUDB:runmode_enable\ SETUP 3.510
Clock Skew 0.000
\PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_AUDIO:PWMUDB:prevCompare1\/main_0 120.337 MHz 8.310 75.023
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell13 U(1,1) 1 \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\ \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/clock \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_AUDIO:PWMUDB:cmp1_less\ \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_AUDIO:PWMUDB:prevCompare1\/main_0 2.290
macrocell116 U(1,1) 1 \PWM_AUDIO:PWMUDB:prevCompare1\ SETUP 3.510
Clock Skew 0.000
\PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_AUDIO:PWMUDB:status_0\/main_1 120.337 MHz 8.310 75.023
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell13 U(1,1) 1 \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\ \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/clock \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_AUDIO:PWMUDB:cmp1_less\ \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_AUDIO:PWMUDB:status_0\/main_1 2.290
macrocell118 U(1,1) 1 \PWM_AUDIO:PWMUDB:status_0\ SETUP 3.510
Clock Skew 0.000
\PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_1678/main_1 120.337 MHz 8.310 75.023
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell13 U(1,1) 1 \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\ \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/clock \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cl0_comb 2.510
Route 1 \PWM_AUDIO:PWMUDB:cmp1_less\ \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_1678/main_1 2.290
macrocell120 U(1,1) 1 Net_1678 SETUP 3.510
Clock Skew 0.000
\PWM_AUDIO:PWMUDB:runmode_enable\/q Net_1678/main_0 125.000 MHz 8.000 75.333
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell115 U(1,1) 1 \PWM_AUDIO:PWMUDB:runmode_enable\ \PWM_AUDIO:PWMUDB:runmode_enable\/clock_0 \PWM_AUDIO:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_AUDIO:PWMUDB:runmode_enable\ \PWM_AUDIO:PWMUDB:runmode_enable\/q Net_1678/main_0 3.240
macrocell120 U(1,1) 1 Net_1678 SETUP 3.510
Clock Skew 0.000
\PWM_AUDIO:PWMUDB:runmode_enable\/q Net_1679/main_0 125.000 MHz 8.000 75.333
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell115 U(1,1) 1 \PWM_AUDIO:PWMUDB:runmode_enable\ \PWM_AUDIO:PWMUDB:runmode_enable\/clock_0 \PWM_AUDIO:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_AUDIO:PWMUDB:runmode_enable\ \PWM_AUDIO:PWMUDB:runmode_enable\/q Net_1679/main_0 3.240
macrocell121 U(1,1) 1 Net_1679 SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 83.3333ns(12 MHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\SPIM_SD:BSPIM:state_2\/q \SPIM_SD:BSPIM:TxStsReg\/status_0 61.927 MHz 16.148 67.185
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell123 U(3,0) 1 \SPIM_SD:BSPIM:state_2\ \SPIM_SD:BSPIM:state_2\/clock_0 \SPIM_SD:BSPIM:state_2\/q 1.250
Route 1 \SPIM_SD:BSPIM:state_2\ \SPIM_SD:BSPIM:state_2\/q \SPIM_SD:BSPIM:tx_status_0\/main_0 5.159
macrocell43 U(3,0) 1 \SPIM_SD:BSPIM:tx_status_0\ \SPIM_SD:BSPIM:tx_status_0\/main_0 \SPIM_SD:BSPIM:tx_status_0\/q 3.350
Route 1 \SPIM_SD:BSPIM:tx_status_0\ \SPIM_SD:BSPIM:tx_status_0\/q \SPIM_SD:BSPIM:TxStsReg\/status_0 5.889
statusicell10 U(3,0) 1 \SPIM_SD:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM_ETH:BSPIM:BitCounter\/count_3 \SPIM_ETH:BSPIM:TxStsReg\/status_3 64.495 MHz 15.505 67.828
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \SPIM_ETH:BSPIM:BitCounter\ \SPIM_ETH:BSPIM:BitCounter\/clock \SPIM_ETH:BSPIM:BitCounter\/count_3 1.940
Route 1 \SPIM_ETH:BSPIM:count_3\ \SPIM_ETH:BSPIM:BitCounter\/count_3 \SPIM_ETH:BSPIM:load_rx_data\/main_1 2.804
macrocell46 U(3,2) 1 \SPIM_ETH:BSPIM:load_rx_data\ \SPIM_ETH:BSPIM:load_rx_data\/main_1 \SPIM_ETH:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_ETH:BSPIM:load_rx_data\ \SPIM_ETH:BSPIM:load_rx_data\/q \SPIM_ETH:BSPIM:TxStsReg\/status_3 6.911
statusicell12 U(3,1) 1 \SPIM_ETH:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM_ETH:BSPIM:BitCounter\/count_4 \SPIM_ETH:BSPIM:TxStsReg\/status_3 64.512 MHz 15.501 67.832
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \SPIM_ETH:BSPIM:BitCounter\ \SPIM_ETH:BSPIM:BitCounter\/clock \SPIM_ETH:BSPIM:BitCounter\/count_4 1.940
Route 1 \SPIM_ETH:BSPIM:count_4\ \SPIM_ETH:BSPIM:BitCounter\/count_4 \SPIM_ETH:BSPIM:load_rx_data\/main_0 2.800
macrocell46 U(3,2) 1 \SPIM_ETH:BSPIM:load_rx_data\ \SPIM_ETH:BSPIM:load_rx_data\/main_0 \SPIM_ETH:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_ETH:BSPIM:load_rx_data\ \SPIM_ETH:BSPIM:load_rx_data\/q \SPIM_ETH:BSPIM:TxStsReg\/status_3 6.911
statusicell12 U(3,1) 1 \SPIM_ETH:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM_ETH:BSPIM:BitCounter\/count_0 \SPIM_ETH:BSPIM:TxStsReg\/status_3 65.266 MHz 15.322 68.011
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \SPIM_ETH:BSPIM:BitCounter\ \SPIM_ETH:BSPIM:BitCounter\/clock \SPIM_ETH:BSPIM:BitCounter\/count_0 1.940
Route 1 \SPIM_ETH:BSPIM:count_0\ \SPIM_ETH:BSPIM:BitCounter\/count_0 \SPIM_ETH:BSPIM:load_rx_data\/main_4 2.621
macrocell46 U(3,2) 1 \SPIM_ETH:BSPIM:load_rx_data\ \SPIM_ETH:BSPIM:load_rx_data\/main_4 \SPIM_ETH:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_ETH:BSPIM:load_rx_data\ \SPIM_ETH:BSPIM:load_rx_data\/q \SPIM_ETH:BSPIM:TxStsReg\/status_3 6.911
statusicell12 U(3,1) 1 \SPIM_ETH:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM_ETH:BSPIM:BitCounter\/count_1 \SPIM_ETH:BSPIM:TxStsReg\/status_3 65.283 MHz 15.318 68.015
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \SPIM_ETH:BSPIM:BitCounter\ \SPIM_ETH:BSPIM:BitCounter\/clock \SPIM_ETH:BSPIM:BitCounter\/count_1 1.940
Route 1 \SPIM_ETH:BSPIM:count_1\ \SPIM_ETH:BSPIM:BitCounter\/count_1 \SPIM_ETH:BSPIM:load_rx_data\/main_3 2.617
macrocell46 U(3,2) 1 \SPIM_ETH:BSPIM:load_rx_data\ \SPIM_ETH:BSPIM:load_rx_data\/main_3 \SPIM_ETH:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_ETH:BSPIM:load_rx_data\ \SPIM_ETH:BSPIM:load_rx_data\/q \SPIM_ETH:BSPIM:TxStsReg\/status_3 6.911
statusicell12 U(3,1) 1 \SPIM_ETH:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM_ETH:BSPIM:BitCounter\/count_2 \SPIM_ETH:BSPIM:TxStsReg\/status_3 65.291 MHz 15.316 68.017
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \SPIM_ETH:BSPIM:BitCounter\ \SPIM_ETH:BSPIM:BitCounter\/clock \SPIM_ETH:BSPIM:BitCounter\/count_2 1.940
Route 1 \SPIM_ETH:BSPIM:count_2\ \SPIM_ETH:BSPIM:BitCounter\/count_2 \SPIM_ETH:BSPIM:load_rx_data\/main_2 2.615
macrocell46 U(3,2) 1 \SPIM_ETH:BSPIM:load_rx_data\ \SPIM_ETH:BSPIM:load_rx_data\/main_2 \SPIM_ETH:BSPIM:load_rx_data\/q 3.350
Route 1 \SPIM_ETH:BSPIM:load_rx_data\ \SPIM_ETH:BSPIM:load_rx_data\/q \SPIM_ETH:BSPIM:TxStsReg\/status_3 6.911
statusicell12 U(3,1) 1 \SPIM_ETH:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM_SD:BSPIM:state_1\/q \SPIM_SD:BSPIM:TxStsReg\/status_0 65.824 MHz 15.192 68.141
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell124 U(3,0) 1 \SPIM_SD:BSPIM:state_1\ \SPIM_SD:BSPIM:state_1\/clock_0 \SPIM_SD:BSPIM:state_1\/q 1.250
Route 1 \SPIM_SD:BSPIM:state_1\ \SPIM_SD:BSPIM:state_1\/q \SPIM_SD:BSPIM:tx_status_0\/main_1 4.203
macrocell43 U(3,0) 1 \SPIM_SD:BSPIM:tx_status_0\ \SPIM_SD:BSPIM:tx_status_0\/main_1 \SPIM_SD:BSPIM:tx_status_0\/q 3.350
Route 1 \SPIM_SD:BSPIM:tx_status_0\ \SPIM_SD:BSPIM:tx_status_0\/q \SPIM_SD:BSPIM:TxStsReg\/status_0 5.889
statusicell10 U(3,0) 1 \SPIM_SD:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM_SD:BSPIM:state_0\/q \SPIM_SD:BSPIM:TxStsReg\/status_0 66.476 MHz 15.043 68.290
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell125 U(2,0) 1 \SPIM_SD:BSPIM:state_0\ \SPIM_SD:BSPIM:state_0\/clock_0 \SPIM_SD:BSPIM:state_0\/q 1.250
Route 1 \SPIM_SD:BSPIM:state_0\ \SPIM_SD:BSPIM:state_0\/q \SPIM_SD:BSPIM:tx_status_0\/main_2 4.054
macrocell43 U(3,0) 1 \SPIM_SD:BSPIM:tx_status_0\ \SPIM_SD:BSPIM:tx_status_0\/main_2 \SPIM_SD:BSPIM:tx_status_0\/q 3.350
Route 1 \SPIM_SD:BSPIM:tx_status_0\ \SPIM_SD:BSPIM:tx_status_0\/q \SPIM_SD:BSPIM:TxStsReg\/status_0 5.889
statusicell10 U(3,0) 1 \SPIM_SD:BSPIM:TxStsReg\ SETUP 0.500
Clock Skew 0.000
\SPIM_SD:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb \SPIM_SD:BSPIM:state_2\/main_8 67.445 MHz 14.827 68.506
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell14 U(3,1) 1 \SPIM_SD:BSPIM:sR8:Dp:u0\ \SPIM_SD:BSPIM:sR8:Dp:u0\/clock \SPIM_SD:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb 3.580
Route 1 \SPIM_SD:BSPIM:tx_status_1\ \SPIM_SD:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb \SPIM_SD:BSPIM:state_2\/main_8 7.737
macrocell123 U(3,0) 1 \SPIM_SD:BSPIM:state_2\ SETUP 3.510
Clock Skew 0.000
\SPIM_SD:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb \SPIM_SD:BSPIM:state_1\/main_8 67.445 MHz 14.827 68.506
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell14 U(3,1) 1 \SPIM_SD:BSPIM:sR8:Dp:u0\ \SPIM_SD:BSPIM:sR8:Dp:u0\/clock \SPIM_SD:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb 3.580
Route 1 \SPIM_SD:BSPIM:tx_status_1\ \SPIM_SD:BSPIM:sR8:Dp:u0\/f0_blk_stat_comb \SPIM_SD:BSPIM:state_1\/main_8 7.737
macrocell124 U(3,0) 1 \SPIM_SD:BSPIM:state_1\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 58.851 MHz 16.992 24.675
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P5[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.805
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_0 5.118
macrocell7 U(0,0) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_0 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.249
datapathcell3 U(0,0) 1 \UART_1:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_5 81.327 MHz 12.296 29.371
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P5[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.805
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_5 5.981
macrocell60 U(0,1) 1 \UART_1:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 81.327 MHz 12.296 29.371
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P5[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.805
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 5.981
macrocell66 U(0,1) 1 \UART_1:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_5 87.313 MHz 11.453 30.214
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P5[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.805
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_5 5.138
macrocell57 U(0,0) 1 \UART_1:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_5 87.313 MHz 11.453 30.214
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P5[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.805
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_5 5.138
macrocell65 U(0,0) 1 \UART_1:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb MODIN1_1/main_2 87.466 MHz 11.433 30.234
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P5[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.805
Route 1 Net_7 Rx_1(0)/fb MODIN1_1/main_2 5.118
macrocell63 U(0,0) 1 MODIN1_1 SETUP 3.510
Clock Skew 0.000
Rx_1(0)/fb MODIN1_0/main_2 87.466 MHz 11.433 30.234
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P5[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.805
Route 1 Net_7 Rx_1(0)/fb MODIN1_0/main_2 5.118
macrocell64 U(0,0) 1 MODIN1_0 SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_2(0)/fb \UART_2:BUART:sRX:RxShifter:u0\/route_si 63.223 MHz 15.817 25.850
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P2[4] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.035
Route 1 Net_1608 Rx_2(0)/fb \UART_2:BUART:rx_postpoll\/main_0 4.653
macrocell17 U(0,4) 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/main_0 \UART_2:BUART:rx_postpoll\/q 3.350
Route 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/q \UART_2:BUART:sRX:RxShifter:u0\/route_si 2.309
datapathcell6 U(0,4) 1 \UART_2:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_2(0)/fb \UART_2:BUART:rx_state_2\/main_5 83.119 MHz 12.031 29.636
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P2[4] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.035
Route 1 Net_1608 Rx_2(0)/fb \UART_2:BUART:rx_state_2\/main_5 6.486
macrocell76 U(0,2) 1 \UART_2:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_2(0)/fb \UART_2:BUART:rx_last\/main_0 89.888 MHz 11.125 30.542
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P2[4] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.035
Route 1 Net_1608 Rx_2(0)/fb \UART_2:BUART:rx_last\/main_0 5.580
macrocell82 U(0,5) 1 \UART_2:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx_2(0)/fb \UART_2:BUART:rx_state_0\/main_5 90.025 MHz 11.108 30.559
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P2[4] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.035
Route 1 Net_1608 Rx_2(0)/fb \UART_2:BUART:rx_state_0\/main_5 5.563
macrocell73 U(0,3) 1 \UART_2:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_2(0)/fb \UART_2:BUART:rx_status_3\/main_5 90.025 MHz 11.108 30.559
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P2[4] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.035
Route 1 Net_1608 Rx_2(0)/fb \UART_2:BUART:rx_status_3\/main_5 5.563
macrocell81 U(0,3) 1 \UART_2:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_2(0)/fb MODIN5_1/main_2 98.058 MHz 10.198 31.469
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P2[4] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.035
Route 1 Net_1608 Rx_2(0)/fb MODIN5_1/main_2 4.653
macrocell79 U(0,4) 1 MODIN5_1 SETUP 3.510
Clock Skew 0.000
Rx_2(0)/fb MODIN5_0/main_2 98.058 MHz 10.198 31.469
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P2[4] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.035
Route 1 Net_1608 Rx_2(0)/fb MODIN5_0/main_2 4.653
macrocell80 U(0,4) 1 MODIN5_0 SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_3(0)/fb \UART_3:BUART:sRX:RxShifter:u0\/route_si 55.457 MHz 18.032 23.635
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P2[2] 1 Rx_3(0) Rx_3(0)/in_clock Rx_3(0)/fb 2.503
Route 1 Net_1619 Rx_3(0)/fb \UART_3:BUART:rx_postpoll\/main_0 5.809
macrocell27 U(0,3) 1 \UART_3:BUART:rx_postpoll\ \UART_3:BUART:rx_postpoll\/main_0 \UART_3:BUART:rx_postpoll\/q 3.350
Route 1 \UART_3:BUART:rx_postpoll\ \UART_3:BUART:rx_postpoll\/q \UART_3:BUART:sRX:RxShifter:u0\/route_si 2.900
datapathcell9 U(0,2) 1 \UART_3:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_3(0)/fb \UART_3:BUART:rx_state_2\/main_5 78.438 MHz 12.749 28.918
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P2[2] 1 Rx_3(0) Rx_3(0)/in_clock Rx_3(0)/fb 2.503
Route 1 Net_1619 Rx_3(0)/fb \UART_3:BUART:rx_state_2\/main_5 6.736
macrocell92 U(0,2) 1 \UART_3:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_3(0)/fb MODIN9_1/main_2 84.588 MHz 11.822 29.845
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P2[2] 1 Rx_3(0) Rx_3(0)/in_clock Rx_3(0)/fb 2.503
Route 1 Net_1619 Rx_3(0)/fb MODIN9_1/main_2 5.809
macrocell95 U(0,3) 1 MODIN9_1 SETUP 3.510
Clock Skew 0.000
Rx_3(0)/fb MODIN9_0/main_2 84.588 MHz 11.822 29.845
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P2[2] 1 Rx_3(0) Rx_3(0)/in_clock Rx_3(0)/fb 2.503
Route 1 Net_1619 Rx_3(0)/fb MODIN9_0/main_2 5.809
macrocell96 U(0,3) 1 MODIN9_0 SETUP 3.510
Clock Skew 0.000
Rx_3(0)/fb \UART_3:BUART:rx_state_0\/main_5 90.220 MHz 11.084 30.583
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P2[2] 1 Rx_3(0) Rx_3(0)/in_clock Rx_3(0)/fb 2.503
Route 1 Net_1619 Rx_3(0)/fb \UART_3:BUART:rx_state_0\/main_5 5.071
macrocell89 U(0,4) 1 \UART_3:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_3(0)/fb \UART_3:BUART:rx_status_3\/main_5 90.220 MHz 11.084 30.583
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P2[2] 1 Rx_3(0) Rx_3(0)/in_clock Rx_3(0)/fb 2.503
Route 1 Net_1619 Rx_3(0)/fb \UART_3:BUART:rx_status_3\/main_5 5.071
macrocell97 U(0,4) 1 \UART_3:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_3(0)/fb \UART_3:BUART:rx_last\/main_0 90.220 MHz 11.084 30.583
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P2[2] 1 Rx_3(0) Rx_3(0)/in_clock Rx_3(0)/fb 2.503
Route 1 Net_1619 Rx_3(0)/fb \UART_3:BUART:rx_last\/main_0 5.071
macrocell98 U(0,4) 1 \UART_3:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 41.6667ns(24 MHz)
Affects clock : CyMASTER_CLK
Source Destination FMax Delay (ns) Slack (ns) Violation
Rx_4(0)/fb \UART_4:BUART:sRX:RxShifter:u0\/route_si 61.162 MHz 16.350 25.317
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P2[0] 1 Rx_4(0) Rx_4(0)/in_clock Rx_4(0)/fb 2.187
Route 1 Net_1630 Rx_4(0)/fb \UART_4:BUART:rx_postpoll\/main_1 5.051
macrocell37 U(1,4) 1 \UART_4:BUART:rx_postpoll\ \UART_4:BUART:rx_postpoll\/main_1 \UART_4:BUART:rx_postpoll\/q 3.350
Route 1 \UART_4:BUART:rx_postpoll\ \UART_4:BUART:rx_postpoll\/q \UART_4:BUART:sRX:RxShifter:u0\/route_si 2.292
datapathcell12 U(1,4) 1 \UART_4:BUART:sRX:RxShifter:u0\ SETUP 3.470
Clock Skew 0.000
Rx_4(0)/fb \UART_4:BUART:rx_state_2\/main_8 84.517 MHz 11.832 29.835
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P2[0] 1 Rx_4(0) Rx_4(0)/in_clock Rx_4(0)/fb 2.187
Route 1 Net_1630 Rx_4(0)/fb \UART_4:BUART:rx_state_2\/main_8 6.135
macrocell108 U(1,5) 1 \UART_4:BUART:rx_state_2\ SETUP 3.510
Clock Skew 0.000
Rx_4(0)/fb \UART_4:BUART:rx_state_0\/main_9 84.631 MHz 11.816 29.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P2[0] 1 Rx_4(0) Rx_4(0)/in_clock Rx_4(0)/fb 2.187
Route 1 Net_1630 Rx_4(0)/fb \UART_4:BUART:rx_state_0\/main_9 6.119
macrocell105 U(1,5) 1 \UART_4:BUART:rx_state_0\ SETUP 3.510
Clock Skew 0.000
Rx_4(0)/fb \UART_4:BUART:rx_status_3\/main_6 84.631 MHz 11.816 29.851
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P2[0] 1 Rx_4(0) Rx_4(0)/in_clock Rx_4(0)/fb 2.187
Route 1 Net_1630 Rx_4(0)/fb \UART_4:BUART:rx_status_3\/main_6 6.119
macrocell113 U(1,5) 1 \UART_4:BUART:rx_status_3\ SETUP 3.510
Clock Skew 0.000
Rx_4(0)/fb \UART_4:BUART:rx_last\/main_0 86.949 MHz 11.501 30.166
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P2[0] 1 Rx_4(0) Rx_4(0)/in_clock Rx_4(0)/fb 2.187
Route 1 Net_1630 Rx_4(0)/fb \UART_4:BUART:rx_last\/main_0 5.804
macrocell114 U(1,3) 1 \UART_4:BUART:rx_last\ SETUP 3.510
Clock Skew 0.000
Rx_4(0)/fb \UART_4:BUART:pollcount_1\/main_3 93.041 MHz 10.748 30.919
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P2[0] 1 Rx_4(0) Rx_4(0)/in_clock Rx_4(0)/fb 2.187
Route 1 Net_1630 Rx_4(0)/fb \UART_4:BUART:pollcount_1\/main_3 5.051
macrocell111 U(1,4) 1 \UART_4:BUART:pollcount_1\ SETUP 3.510
Clock Skew 0.000
Rx_4(0)/fb \UART_4:BUART:pollcount_0\/main_2 93.041 MHz 10.748 30.919
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P2[0] 1 Rx_4(0) Rx_4(0)/in_clock Rx_4(0)/fb 2.187
Route 1 Net_1630 Rx_4(0)/fb \UART_4:BUART:pollcount_0\/main_2 5.051
macrocell112 U(1,4) 1 \UART_4:BUART:pollcount_0\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sTX:TxSts\/status_0 55.276 MHz 18.091 1065.242
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell1 U(2,1) 1 \UART_1:BUART:sTX:TxShifter:u0\ \UART_1:BUART:sTX:TxShifter:u0\/clock \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART_1:BUART:tx_fifo_empty\ \UART_1:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:tx_status_0\/main_2 3.822
macrocell4 U(2,1) 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/main_2 \UART_1:BUART:tx_status_0\/q 3.350
Route 1 \UART_1:BUART:tx_status_0\ \UART_1:BUART:tx_status_0\/q \UART_1:BUART:sTX:TxSts\/status_0 6.839
statusicell1 U(1,2) 1 \UART_1:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
\UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 57.418 MHz 17.416 1065.917
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell2 U(2,2) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb 2.510
Route 1 \UART_1:BUART:tx_bitclk_dp\ \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_1:BUART:tx_bitclk_enable_pre\/main_0 2.626
macrocell3 U(2,2) 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/main_0 \UART_1:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART_1:BUART:tx_bitclk_enable_pre\ \UART_1:BUART:tx_bitclk_enable_pre\/q \UART_1:BUART:sTX:TxShifter:u0\/cs_addr_0 2.920
datapathcell1 U(2,1) 1 \UART_1:BUART:sTX:TxShifter:u0\ SETUP 6.010
Clock Skew 0.000
\UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:sRX:RxSts\/status_4 58.713 MHz 17.032 1066.301
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell3 U(0,0) 1 \UART_1:BUART:sRX:RxShifter:u0\ \UART_1:BUART:sRX:RxShifter:u0\/clock \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART_1:BUART:rx_fifofull\ \UART_1:BUART:sRX:RxShifter:u0\/f0_blk_stat_comb \UART_1:BUART:rx_status_4\/main_1 2.247
macrocell8 U(1,0) 1 \UART_1:BUART:rx_status_4\ \UART_1:BUART:rx_status_4\/main_1 \UART_1:BUART:rx_status_4\/q 3.350
Route 1 \UART_1:BUART:rx_status_4\ \UART_1:BUART:rx_status_4\/q \UART_1:BUART:sRX:RxSts\/status_4 7.355
statusicell2 U(0,5) 1 \UART_1:BUART:sRX:RxSts\ SETUP 0.500
Clock Skew 0.000
\UART_1:BUART:tx_state_1\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 59.495 MHz 16.808 1066.525
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell52 U(2,1) 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/clock_0 \UART_1:BUART:tx_state_1\/q 1.250
Route 1 \UART_1:BUART:tx_state_1\ \UART_1:BUART:tx_state_1\/q \UART_1:BUART:counter_load_not\/main_0 3.099
macrocell2 U(2,1) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_0 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.919
datapathcell2 U(2,2) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_state_0\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 59.542 MHz 16.795 1066.538
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell53 U(2,1) 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/clock_0 \UART_1:BUART:tx_state_0\/q 1.250
Route 1 \UART_1:BUART:tx_state_0\ \UART_1:BUART:tx_state_0\/q \UART_1:BUART:counter_load_not\/main_1 3.086
macrocell2 U(2,1) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_1 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.919
datapathcell2 U(2,2) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_bitclk\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 60.129 MHz 16.631 1066.702
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell55 U(2,1) 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/clock_0 \UART_1:BUART:tx_bitclk\/q 1.250
Route 1 \UART_1:BUART:tx_bitclk\ \UART_1:BUART:tx_bitclk\/q \UART_1:BUART:counter_load_not\/main_3 2.922
macrocell2 U(2,1) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_3 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.919
datapathcell2 U(2,2) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:rx_state_0\/q \UART_1:BUART:sRX:RxBitCounter\/load 60.775 MHz 16.454 1066.879
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell57 U(0,0) 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/clock_0 \UART_1:BUART:rx_state_0\/q 1.250
Route 1 \UART_1:BUART:rx_state_0\ \UART_1:BUART:rx_state_0\/q \UART_1:BUART:rx_counter_load\/main_1 3.625
macrocell6 U(0,1) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_1 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.869
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:tx_state_2\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 61.293 MHz 16.315 1067.018
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell54 U(2,1) 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/clock_0 \UART_1:BUART:tx_state_2\/q 1.250
Route 1 \UART_1:BUART:tx_state_2\ \UART_1:BUART:tx_state_2\/q \UART_1:BUART:counter_load_not\/main_2 2.606
macrocell2 U(2,1) 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/main_2 \UART_1:BUART:counter_load_not\/q 3.350
Route 1 \UART_1:BUART:counter_load_not\ \UART_1:BUART:counter_load_not\/q \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.919
datapathcell2 U(2,2) 1 \UART_1:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:sRX:RxBitCounter\/load 63.496 MHz 15.749 1067.584
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell56 U(1,2) 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/clock_0 \UART_1:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART_1:BUART:tx_ctrl_mark_last\ \UART_1:BUART:tx_ctrl_mark_last\/q \UART_1:BUART:rx_counter_load\/main_0 2.920
macrocell6 U(0,1) 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/main_0 \UART_1:BUART:rx_counter_load\/q 3.350
Route 1 \UART_1:BUART:rx_counter_load\ \UART_1:BUART:rx_counter_load\/q \UART_1:BUART:sRX:RxBitCounter\/load 2.869
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_1:BUART:rx_load_fifo\/q \UART_1:BUART:sRX:RxSts\/status_4 66.041 MHz 15.142 1068.191
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell58 U(0,0) 1 \UART_1:BUART:rx_load_fifo\ \UART_1:BUART:rx_load_fifo\/clock_0 \UART_1:BUART:rx_load_fifo\/q 1.250
Route 1 \UART_1:BUART:rx_load_fifo\ \UART_1:BUART:rx_load_fifo\/q \UART_1:BUART:rx_status_4\/main_0 2.687
macrocell8 U(1,0) 1 \UART_1:BUART:rx_status_4\ \UART_1:BUART:rx_status_4\/main_0 \UART_1:BUART:rx_status_4\/q 3.350
Route 1 \UART_1:BUART:rx_status_4\ \UART_1:BUART:rx_status_4\/q \UART_1:BUART:sRX:RxSts\/status_4 7.355
statusicell2 U(0,5) 1 \UART_1:BUART:sRX:RxSts\ SETUP 0.500
Clock Skew 0.000
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_2:BUART:sTX:TxShifter:u0\/cs_addr_0 45.323 MHz 22.064 1061.269
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(1,3) 1 \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb 2.510
Route 1 \UART_2:BUART:tx_bitclk_dp\ \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_2:BUART:tx_bitclk_enable_pre\/main_0 6.515
macrocell13 U(2,3) 1 \UART_2:BUART:tx_bitclk_enable_pre\ \UART_2:BUART:tx_bitclk_enable_pre\/main_0 \UART_2:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART_2:BUART:tx_bitclk_enable_pre\ \UART_2:BUART:tx_bitclk_enable_pre\/q \UART_2:BUART:sTX:TxShifter:u0\/cs_addr_0 3.679
datapathcell4 U(3,5) 1 \UART_2:BUART:sTX:TxShifter:u0\ SETUP 6.010
Clock Skew 0.000
\UART_2:BUART:tx_bitclk\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 45.750 MHz 21.858 1061.475
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell71 U(2,5) 1 \UART_2:BUART:tx_bitclk\ \UART_2:BUART:tx_bitclk\/clock_0 \UART_2:BUART:tx_bitclk\/q 1.250
Route 1 \UART_2:BUART:tx_bitclk\ \UART_2:BUART:tx_bitclk\/q \UART_2:BUART:counter_load_not\/main_3 3.503
macrocell12 U(3,5) 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/main_3 \UART_2:BUART:counter_load_not\/q 3.350
Route 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 7.565
datapathcell5 U(1,3) 1 \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_2:BUART:tx_state_0\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 45.950 MHz 21.763 1061.570
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell69 U(3,5) 1 \UART_2:BUART:tx_state_0\ \UART_2:BUART:tx_state_0\/clock_0 \UART_2:BUART:tx_state_0\/q 1.250
Route 1 \UART_2:BUART:tx_state_0\ \UART_2:BUART:tx_state_0\/q \UART_2:BUART:counter_load_not\/main_1 3.408
macrocell12 U(3,5) 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/main_1 \UART_2:BUART:counter_load_not\/q 3.350
Route 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 7.565
datapathcell5 U(1,3) 1 \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_2:BUART:tx_state_1\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.034 MHz 21.723 1061.610
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell68 U(3,5) 1 \UART_2:BUART:tx_state_1\ \UART_2:BUART:tx_state_1\/clock_0 \UART_2:BUART:tx_state_1\/q 1.250
Route 1 \UART_2:BUART:tx_state_1\ \UART_2:BUART:tx_state_1\/q \UART_2:BUART:counter_load_not\/main_0 3.368
macrocell12 U(3,5) 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/main_0 \UART_2:BUART:counter_load_not\/q 3.350
Route 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 7.565
datapathcell5 U(1,3) 1 \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_2:BUART:tx_state_2\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 46.668 MHz 21.428 1061.905
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell70 U(3,5) 1 \UART_2:BUART:tx_state_2\ \UART_2:BUART:tx_state_2\/clock_0 \UART_2:BUART:tx_state_2\/q 1.250
Route 1 \UART_2:BUART:tx_state_2\ \UART_2:BUART:tx_state_2\/q \UART_2:BUART:counter_load_not\/main_2 3.073
macrocell12 U(3,5) 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/main_2 \UART_2:BUART:counter_load_not\/q 3.350
Route 1 \UART_2:BUART:counter_load_not\ \UART_2:BUART:counter_load_not\/q \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 7.565
datapathcell5 U(1,3) 1 \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_2:BUART:tx_ctrl_mark_last\/q \UART_2:BUART:sRX:RxBitCounter\/load 52.723 MHz 18.967 1064.366
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell72 U(0,5) 1 \UART_2:BUART:tx_ctrl_mark_last\ \UART_2:BUART:tx_ctrl_mark_last\/clock_0 \UART_2:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART_2:BUART:tx_ctrl_mark_last\ \UART_2:BUART:tx_ctrl_mark_last\/q \UART_2:BUART:rx_counter_load\/main_0 6.678
macrocell16 U(0,3) 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/main_0 \UART_2:BUART:rx_counter_load\/q 3.350
Route 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/q \UART_2:BUART:sRX:RxBitCounter\/load 2.329
count7cell U(0,3) 1 \UART_2:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_2:BUART:rx_state_0\/q \UART_2:BUART:sRX:RxBitCounter\/load 60.987 MHz 16.397 1066.936
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell73 U(0,3) 1 \UART_2:BUART:rx_state_0\ \UART_2:BUART:rx_state_0\/clock_0 \UART_2:BUART:rx_state_0\/q 1.250
Route 1 \UART_2:BUART:rx_state_0\ \UART_2:BUART:rx_state_0\/q \UART_2:BUART:rx_counter_load\/main_1 4.108
macrocell16 U(0,3) 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/main_1 \UART_2:BUART:rx_counter_load\/q 3.350
Route 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/q \UART_2:BUART:sRX:RxBitCounter\/load 2.329
count7cell U(0,3) 1 \UART_2:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_2:BUART:rx_state_2\/q \UART_2:BUART:sRX:RxBitCounter\/load 64.466 MHz 15.512 1067.821
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell76 U(0,2) 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/clock_0 \UART_2:BUART:rx_state_2\/q 1.250
Route 1 \UART_2:BUART:rx_state_2\ \UART_2:BUART:rx_state_2\/q \UART_2:BUART:rx_counter_load\/main_3 3.223
macrocell16 U(0,3) 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/main_3 \UART_2:BUART:rx_counter_load\/q 3.350
Route 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/q \UART_2:BUART:sRX:RxBitCounter\/load 2.329
count7cell U(0,3) 1 \UART_2:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_2:BUART:rx_state_3\/q \UART_2:BUART:sRX:RxBitCounter\/load 64.475 MHz 15.510 1067.823
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell75 U(0,2) 1 \UART_2:BUART:rx_state_3\ \UART_2:BUART:rx_state_3\/clock_0 \UART_2:BUART:rx_state_3\/q 1.250
Route 1 \UART_2:BUART:rx_state_3\ \UART_2:BUART:rx_state_3\/q \UART_2:BUART:rx_counter_load\/main_2 3.221
macrocell16 U(0,3) 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/main_2 \UART_2:BUART:rx_counter_load\/q 3.350
Route 1 \UART_2:BUART:rx_counter_load\ \UART_2:BUART:rx_counter_load\/q \UART_2:BUART:sRX:RxBitCounter\/load 2.329
count7cell U(0,3) 1 \UART_2:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_2:BUART:tx_bitclk\/main_0 71.185 MHz 14.048 1069.285
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell5 U(1,3) 1 \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb 2.510
Route 1 \UART_2:BUART:tx_bitclk_dp\ \UART_2:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_2:BUART:tx_bitclk\/main_0 8.028
macrocell71 U(2,5) 1 \UART_2:BUART:tx_bitclk\ SETUP 3.510
Clock Skew 0.000
Path Delay Requirement : 2166.67ns(461.538 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_3:BUART:rx_state_3\/q \UART_3:BUART:sRX:RxBitCounter\/load 50.201 MHz 19.920 2146.747
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell91 U(0,4) 1 \UART_3:BUART:rx_state_3\ \UART_3:BUART:rx_state_3\/clock_0 \UART_3:BUART:rx_state_3\/q 1.250
Route 1 \UART_3:BUART:rx_state_3\ \UART_3:BUART:rx_state_3\/q \UART_3:BUART:rx_counter_load\/main_2 7.633
macrocell26 U(0,2) 1 \UART_3:BUART:rx_counter_load\ \UART_3:BUART:rx_counter_load\/main_2 \UART_3:BUART:rx_counter_load\/q 3.350
Route 1 \UART_3:BUART:rx_counter_load\ \UART_3:BUART:rx_counter_load\/q \UART_3:BUART:sRX:RxBitCounter\/load 2.327
count7cell U(0,2) 1 \UART_3:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_3:BUART:tx_state_2\/q \UART_3:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 56.044 MHz 17.843 2148.824
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell86 U(3,3) 1 \UART_3:BUART:tx_state_2\ \UART_3:BUART:tx_state_2\/clock_0 \UART_3:BUART:tx_state_2\/q 1.250
Route 1 \UART_3:BUART:tx_state_2\ \UART_3:BUART:tx_state_2\/q \UART_3:BUART:counter_load_not\/main_2 4.145
macrocell22 U(3,5) 1 \UART_3:BUART:counter_load_not\ \UART_3:BUART:counter_load_not\/main_2 \UART_3:BUART:counter_load_not\/q 3.350
Route 1 \UART_3:BUART:counter_load_not\ \UART_3:BUART:counter_load_not\/q \UART_3:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.908
datapathcell8 U(3,4) 1 \UART_3:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_3:BUART:tx_state_1\/q \UART_3:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 58.469 MHz 17.103 2149.564
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell84 U(3,4) 1 \UART_3:BUART:tx_state_1\ \UART_3:BUART:tx_state_1\/clock_0 \UART_3:BUART:tx_state_1\/q 1.250
Route 1 \UART_3:BUART:tx_state_1\ \UART_3:BUART:tx_state_1\/q \UART_3:BUART:counter_load_not\/main_0 3.405
macrocell22 U(3,5) 1 \UART_3:BUART:counter_load_not\ \UART_3:BUART:counter_load_not\/main_0 \UART_3:BUART:counter_load_not\/q 3.350
Route 1 \UART_3:BUART:counter_load_not\ \UART_3:BUART:counter_load_not\/q \UART_3:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.908
datapathcell8 U(3,4) 1 \UART_3:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_3:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_3:BUART:sTX:TxShifter:u0\/cs_addr_0 58.524 MHz 17.087 2149.580
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell8 U(3,4) 1 \UART_3:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_3:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_3:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb 2.510
Route 1 \UART_3:BUART:tx_bitclk_dp\ \UART_3:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_3:BUART:tx_bitclk_enable_pre\/main_0 2.303
macrocell23 U(3,4) 1 \UART_3:BUART:tx_bitclk_enable_pre\ \UART_3:BUART:tx_bitclk_enable_pre\/main_0 \UART_3:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART_3:BUART:tx_bitclk_enable_pre\ \UART_3:BUART:tx_bitclk_enable_pre\/q \UART_3:BUART:sTX:TxShifter:u0\/cs_addr_0 2.914
datapathcell7 U(3,3) 1 \UART_3:BUART:sTX:TxShifter:u0\ SETUP 6.010
Clock Skew 0.000
\UART_3:BUART:rx_state_0\/q \UART_3:BUART:sRX:RxBitCounter\/load 59.060 MHz 16.932 2149.735
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell89 U(0,4) 1 \UART_3:BUART:rx_state_0\ \UART_3:BUART:rx_state_0\/clock_0 \UART_3:BUART:rx_state_0\/q 1.250
Route 1 \UART_3:BUART:rx_state_0\ \UART_3:BUART:rx_state_0\/q \UART_3:BUART:rx_counter_load\/main_1 4.645
macrocell26 U(0,2) 1 \UART_3:BUART:rx_counter_load\ \UART_3:BUART:rx_counter_load\/main_1 \UART_3:BUART:rx_counter_load\/q 3.350
Route 1 \UART_3:BUART:rx_counter_load\ \UART_3:BUART:rx_counter_load\/q \UART_3:BUART:sRX:RxBitCounter\/load 2.327
count7cell U(0,2) 1 \UART_3:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_3:BUART:tx_bitclk\/q \UART_3:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 59.116 MHz 16.916 2149.751
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell87 U(3,4) 1 \UART_3:BUART:tx_bitclk\ \UART_3:BUART:tx_bitclk\/clock_0 \UART_3:BUART:tx_bitclk\/q 1.250
Route 1 \UART_3:BUART:tx_bitclk\ \UART_3:BUART:tx_bitclk\/q \UART_3:BUART:counter_load_not\/main_3 3.218
macrocell22 U(3,5) 1 \UART_3:BUART:counter_load_not\ \UART_3:BUART:counter_load_not\/main_3 \UART_3:BUART:counter_load_not\/q 3.350
Route 1 \UART_3:BUART:counter_load_not\ \UART_3:BUART:counter_load_not\/q \UART_3:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.908
datapathcell8 U(3,4) 1 \UART_3:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_3:BUART:tx_state_0\/q \UART_3:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 59.172 MHz 16.900 2149.767
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell85 U(3,4) 1 \UART_3:BUART:tx_state_0\ \UART_3:BUART:tx_state_0\/clock_0 \UART_3:BUART:tx_state_0\/q 1.250
Route 1 \UART_3:BUART:tx_state_0\ \UART_3:BUART:tx_state_0\/q \UART_3:BUART:counter_load_not\/main_1 3.202
macrocell22 U(3,5) 1 \UART_3:BUART:counter_load_not\ \UART_3:BUART:counter_load_not\/main_1 \UART_3:BUART:counter_load_not\/q 3.350
Route 1 \UART_3:BUART:counter_load_not\ \UART_3:BUART:counter_load_not\/q \UART_3:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.908
datapathcell8 U(3,4) 1 \UART_3:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_3:BUART:tx_ctrl_mark_last\/q \UART_3:BUART:sRX:RxBitCounter\/load 62.139 MHz 16.093 2150.574
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell88 U(0,1) 1 \UART_3:BUART:tx_ctrl_mark_last\ \UART_3:BUART:tx_ctrl_mark_last\/clock_0 \UART_3:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART_3:BUART:tx_ctrl_mark_last\ \UART_3:BUART:tx_ctrl_mark_last\/q \UART_3:BUART:rx_counter_load\/main_0 3.806
macrocell26 U(0,2) 1 \UART_3:BUART:rx_counter_load\ \UART_3:BUART:rx_counter_load\/main_0 \UART_3:BUART:rx_counter_load\/q 3.350
Route 1 \UART_3:BUART:rx_counter_load\ \UART_3:BUART:rx_counter_load\/q \UART_3:BUART:sRX:RxBitCounter\/load 2.327
count7cell U(0,2) 1 \UART_3:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_3:BUART:rx_state_2\/q \UART_3:BUART:sRX:RxBitCounter\/load 64.508 MHz 15.502 2151.165
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell92 U(0,2) 1 \UART_3:BUART:rx_state_2\ \UART_3:BUART:rx_state_2\/clock_0 \UART_3:BUART:rx_state_2\/q 1.250
Route 1 \UART_3:BUART:rx_state_2\ \UART_3:BUART:rx_state_2\/q \UART_3:BUART:rx_counter_load\/main_3 3.215
macrocell26 U(0,2) 1 \UART_3:BUART:rx_counter_load\ \UART_3:BUART:rx_counter_load\/main_3 \UART_3:BUART:rx_counter_load\/q 3.350
Route 1 \UART_3:BUART:rx_counter_load\ \UART_3:BUART:rx_counter_load\/q \UART_3:BUART:sRX:RxBitCounter\/load 2.327
count7cell U(0,2) 1 \UART_3:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_3:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_3:BUART:sTX:TxSts\/status_0 72.817 MHz 13.733 2152.934
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell7 U(3,3) 1 \UART_3:BUART:sTX:TxShifter:u0\ \UART_3:BUART:sTX:TxShifter:u0\/clock \UART_3:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART_3:BUART:tx_fifo_empty\ \UART_3:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_3:BUART:tx_status_0\/main_2 4.008
macrocell24 U(3,4) 1 \UART_3:BUART:tx_status_0\ \UART_3:BUART:tx_status_0\/main_2 \UART_3:BUART:tx_status_0\/q 3.350
Route 1 \UART_3:BUART:tx_status_0\ \UART_3:BUART:tx_status_0\/q \UART_3:BUART:sTX:TxSts\/status_0 2.295
statusicell5 U(3,4) 1 \UART_3:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
Path Delay Requirement : 1083.33ns(923.077 kHz)
Source Destination FMax Delay (ns) Slack (ns) Violation
\UART_4:BUART:tx_state_0\/q \UART_4:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 54.416 MHz 18.377 1064.956
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell101 U(2,5) 1 \UART_4:BUART:tx_state_0\ \UART_4:BUART:tx_state_0\/clock_0 \UART_4:BUART:tx_state_0\/q 1.250
Route 1 \UART_4:BUART:tx_state_0\ \UART_4:BUART:tx_state_0\/q \UART_4:BUART:counter_load_not\/main_1 4.686
macrocell32 U(2,4) 1 \UART_4:BUART:counter_load_not\ \UART_4:BUART:counter_load_not\/main_1 \UART_4:BUART:counter_load_not\/q 3.350
Route 1 \UART_4:BUART:counter_load_not\ \UART_4:BUART:counter_load_not\/q \UART_4:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.901
datapathcell11 U(2,3) 1 \UART_4:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_4:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_4:BUART:sTX:TxShifter:u0\/cs_addr_0 58.445 MHz 17.110 1066.223
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell11 U(2,3) 1 \UART_4:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_4:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_4:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb 2.510
Route 1 \UART_4:BUART:tx_bitclk_dp\ \UART_4:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_4:BUART:tx_bitclk_enable_pre\/main_0 2.304
macrocell33 U(2,3) 1 \UART_4:BUART:tx_bitclk_enable_pre\ \UART_4:BUART:tx_bitclk_enable_pre\/main_0 \UART_4:BUART:tx_bitclk_enable_pre\/q 3.350
Route 1 \UART_4:BUART:tx_bitclk_enable_pre\ \UART_4:BUART:tx_bitclk_enable_pre\/q \UART_4:BUART:sTX:TxShifter:u0\/cs_addr_0 2.936
datapathcell10 U(2,4) 1 \UART_4:BUART:sTX:TxShifter:u0\ SETUP 6.010
Clock Skew 0.000
\UART_4:BUART:tx_bitclk\/q \UART_4:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 59.659 MHz 16.762 1066.571
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell103 U(2,3) 1 \UART_4:BUART:tx_bitclk\ \UART_4:BUART:tx_bitclk\/clock_0 \UART_4:BUART:tx_bitclk\/q 1.250
Route 1 \UART_4:BUART:tx_bitclk\ \UART_4:BUART:tx_bitclk\/q \UART_4:BUART:counter_load_not\/main_3 3.071
macrocell32 U(2,4) 1 \UART_4:BUART:counter_load_not\ \UART_4:BUART:counter_load_not\/main_3 \UART_4:BUART:counter_load_not\/q 3.350
Route 1 \UART_4:BUART:counter_load_not\ \UART_4:BUART:counter_load_not\/q \UART_4:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.901
datapathcell11 U(2,3) 1 \UART_4:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_4:BUART:tx_state_1\/q \UART_4:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 60.292 MHz 16.586 1066.747
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell100 U(2,4) 1 \UART_4:BUART:tx_state_1\ \UART_4:BUART:tx_state_1\/clock_0 \UART_4:BUART:tx_state_1\/q 1.250
Route 1 \UART_4:BUART:tx_state_1\ \UART_4:BUART:tx_state_1\/q \UART_4:BUART:counter_load_not\/main_0 2.895
macrocell32 U(2,4) 1 \UART_4:BUART:counter_load_not\ \UART_4:BUART:counter_load_not\/main_0 \UART_4:BUART:counter_load_not\/q 3.350
Route 1 \UART_4:BUART:counter_load_not\ \UART_4:BUART:counter_load_not\/q \UART_4:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.901
datapathcell11 U(2,3) 1 \UART_4:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_4:BUART:tx_state_2\/q \UART_4:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 60.661 MHz 16.485 1066.848
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell102 U(2,4) 1 \UART_4:BUART:tx_state_2\ \UART_4:BUART:tx_state_2\/clock_0 \UART_4:BUART:tx_state_2\/q 1.250
Route 1 \UART_4:BUART:tx_state_2\ \UART_4:BUART:tx_state_2\/q \UART_4:BUART:counter_load_not\/main_2 2.794
macrocell32 U(2,4) 1 \UART_4:BUART:counter_load_not\ \UART_4:BUART:counter_load_not\/main_2 \UART_4:BUART:counter_load_not\/q 3.350
Route 1 \UART_4:BUART:counter_load_not\ \UART_4:BUART:counter_load_not\/q \UART_4:BUART:sTX:sCLOCK:TxBitClkGen\/cs_addr_0 2.901
datapathcell11 U(2,3) 1 \UART_4:BUART:sTX:sCLOCK:TxBitClkGen\ SETUP 6.190
Clock Skew 0.000
\UART_4:BUART:rx_state_0\/q \UART_4:BUART:sRX:RxBitCounter\/load 63.532 MHz 15.740 1067.593
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell105 U(1,5) 1 \UART_4:BUART:rx_state_0\ \UART_4:BUART:rx_state_0\/clock_0 \UART_4:BUART:rx_state_0\/q 1.250
Route 1 \UART_4:BUART:rx_state_0\ \UART_4:BUART:rx_state_0\/q \UART_4:BUART:rx_counter_load\/main_1 3.469
macrocell36 U(1,5) 1 \UART_4:BUART:rx_counter_load\ \UART_4:BUART:rx_counter_load\/main_1 \UART_4:BUART:rx_counter_load\/q 3.350
Route 1 \UART_4:BUART:rx_counter_load\ \UART_4:BUART:rx_counter_load\/q \UART_4:BUART:sRX:RxBitCounter\/load 2.311
count7cell U(1,5) 1 \UART_4:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_4:BUART:tx_ctrl_mark_last\/q \UART_4:BUART:sRX:RxBitCounter\/load 66.476 MHz 15.043 1068.290
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell104 U(1,5) 1 \UART_4:BUART:tx_ctrl_mark_last\ \UART_4:BUART:tx_ctrl_mark_last\/clock_0 \UART_4:BUART:tx_ctrl_mark_last\/q 1.250
Route 1 \UART_4:BUART:tx_ctrl_mark_last\ \UART_4:BUART:tx_ctrl_mark_last\/q \UART_4:BUART:rx_counter_load\/main_0 2.772
macrocell36 U(1,5) 1 \UART_4:BUART:rx_counter_load\ \UART_4:BUART:rx_counter_load\/main_0 \UART_4:BUART:rx_counter_load\/q 3.350
Route 1 \UART_4:BUART:rx_counter_load\ \UART_4:BUART:rx_counter_load\/q \UART_4:BUART:sRX:RxBitCounter\/load 2.311
count7cell U(1,5) 1 \UART_4:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_4:BUART:rx_state_3\/q \UART_4:BUART:sRX:RxBitCounter\/load 66.481 MHz 15.042 1068.291
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell107 U(1,5) 1 \UART_4:BUART:rx_state_3\ \UART_4:BUART:rx_state_3\/clock_0 \UART_4:BUART:rx_state_3\/q 1.250
Route 1 \UART_4:BUART:rx_state_3\ \UART_4:BUART:rx_state_3\/q \UART_4:BUART:rx_counter_load\/main_2 2.771
macrocell36 U(1,5) 1 \UART_4:BUART:rx_counter_load\ \UART_4:BUART:rx_counter_load\/main_2 \UART_4:BUART:rx_counter_load\/q 3.350
Route 1 \UART_4:BUART:rx_counter_load\ \UART_4:BUART:rx_counter_load\/q \UART_4:BUART:sRX:RxBitCounter\/load 2.311
count7cell U(1,5) 1 \UART_4:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_4:BUART:rx_state_2\/q \UART_4:BUART:sRX:RxBitCounter\/load 67.354 MHz 14.847 1068.486
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell108 U(1,5) 1 \UART_4:BUART:rx_state_2\ \UART_4:BUART:rx_state_2\/clock_0 \UART_4:BUART:rx_state_2\/q 1.250
Route 1 \UART_4:BUART:rx_state_2\ \UART_4:BUART:rx_state_2\/q \UART_4:BUART:rx_counter_load\/main_3 2.576
macrocell36 U(1,5) 1 \UART_4:BUART:rx_counter_load\ \UART_4:BUART:rx_counter_load\/main_3 \UART_4:BUART:rx_counter_load\/q 3.350
Route 1 \UART_4:BUART:rx_counter_load\ \UART_4:BUART:rx_counter_load\/q \UART_4:BUART:sRX:RxBitCounter\/load 2.311
count7cell U(1,5) 1 \UART_4:BUART:sRX:RxBitCounter\ SETUP 5.360
Clock Skew 0.000
\UART_4:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_4:BUART:sTX:TxSts\/status_0 69.329 MHz 14.424 1068.909
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell10 U(2,4) 1 \UART_4:BUART:sTX:TxShifter:u0\ \UART_4:BUART:sTX:TxShifter:u0\/clock \UART_4:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb 3.580
Route 1 \UART_4:BUART:tx_fifo_empty\ \UART_4:BUART:sTX:TxShifter:u0\/f0_blk_stat_comb \UART_4:BUART:tx_status_0\/main_2 4.085
macrocell34 U(2,5) 1 \UART_4:BUART:tx_status_0\ \UART_4:BUART:tx_status_0\/main_2 \UART_4:BUART:tx_status_0\/q 3.350
Route 1 \UART_4:BUART:tx_status_0\ \UART_4:BUART:tx_status_0\/q \UART_4:BUART:sTX:TxSts\/status_0 2.909
statusicell7 U(2,4) 1 \UART_4:BUART:sTX:TxSts\ SETUP 0.500
Clock Skew 0.000
+ Hold Subsection
Source Destination Slack (ns) Violation
\PWM_AUDIO:PWMUDB:status_0\/q \PWM_AUDIO:PWMUDB:genblk8:stsreg\/status_0 1.545
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell118 U(1,1) 1 \PWM_AUDIO:PWMUDB:status_0\ \PWM_AUDIO:PWMUDB:status_0\/clock_0 \PWM_AUDIO:PWMUDB:status_0\/q 1.250
Route 1 \PWM_AUDIO:PWMUDB:status_0\ \PWM_AUDIO:PWMUDB:status_0\/q \PWM_AUDIO:PWMUDB:genblk8:stsreg\/status_0 2.295
statusicell9 U(1,1) 1 \PWM_AUDIO:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_AUDIO:PWMUDB:status_1\/q \PWM_AUDIO:PWMUDB:genblk8:stsreg\/status_1 1.563
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell119 U(1,1) 1 \PWM_AUDIO:PWMUDB:status_1\ \PWM_AUDIO:PWMUDB:status_1\/clock_0 \PWM_AUDIO:PWMUDB:status_1\/q 1.250
Route 1 \PWM_AUDIO:PWMUDB:status_1\ \PWM_AUDIO:PWMUDB:status_1\/q \PWM_AUDIO:PWMUDB:genblk8:stsreg\/status_1 2.313
statusicell9 U(1,1) 1 \PWM_AUDIO:PWMUDB:genblk8:stsreg\ HOLD -2.000
Clock Skew 0.000
\PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_AUDIO:PWMUDB:prevCompare1\/main_0 3.070
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell13 U(1,1) 1 \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\ \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/clock \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_AUDIO:PWMUDB:cmp1_less\ \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_AUDIO:PWMUDB:prevCompare1\/main_0 2.290
macrocell116 U(1,1) 1 \PWM_AUDIO:PWMUDB:prevCompare1\ HOLD 0.000
Clock Skew 0.000
\PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_AUDIO:PWMUDB:status_0\/main_1 3.070
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell13 U(1,1) 1 \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\ \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/clock \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_AUDIO:PWMUDB:cmp1_less\ \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cl0_comb \PWM_AUDIO:PWMUDB:status_0\/main_1 2.290
macrocell118 U(1,1) 1 \PWM_AUDIO:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_1678/main_1 3.070
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell13 U(1,1) 1 \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\ \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/clock \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cl0_comb 0.780
Route 1 \PWM_AUDIO:PWMUDB:cmp1_less\ \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cl0_comb Net_1678/main_1 2.290
macrocell120 U(1,1) 1 Net_1678 HOLD 0.000
Clock Skew 0.000
\PWM_AUDIO:PWMUDB:prevCompare1\/q \PWM_AUDIO:PWMUDB:status_0\/main_0 3.543
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell116 U(1,1) 1 \PWM_AUDIO:PWMUDB:prevCompare1\ \PWM_AUDIO:PWMUDB:prevCompare1\/clock_0 \PWM_AUDIO:PWMUDB:prevCompare1\/q 1.250
Route 1 \PWM_AUDIO:PWMUDB:prevCompare1\ \PWM_AUDIO:PWMUDB:prevCompare1\/q \PWM_AUDIO:PWMUDB:status_0\/main_0 2.293
macrocell118 U(1,1) 1 \PWM_AUDIO:PWMUDB:status_0\ HOLD 0.000
Clock Skew 0.000
\PWM_AUDIO:PWMUDB:prevCompare2\/q \PWM_AUDIO:PWMUDB:status_1\/main_0 3.560
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell117 U(1,1) 1 \PWM_AUDIO:PWMUDB:prevCompare2\ \PWM_AUDIO:PWMUDB:prevCompare2\/clock_0 \PWM_AUDIO:PWMUDB:prevCompare2\/q 1.250
Route 1 \PWM_AUDIO:PWMUDB:prevCompare2\ \PWM_AUDIO:PWMUDB:prevCompare2\/q \PWM_AUDIO:PWMUDB:status_1\/main_0 2.310
macrocell119 U(1,1) 1 \PWM_AUDIO:PWMUDB:status_1\ HOLD 0.000
Clock Skew 0.000
\PWM_AUDIO:PWMUDB:runmode_enable\/q Net_1678/main_0 4.490
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell115 U(1,1) 1 \PWM_AUDIO:PWMUDB:runmode_enable\ \PWM_AUDIO:PWMUDB:runmode_enable\/clock_0 \PWM_AUDIO:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_AUDIO:PWMUDB:runmode_enable\ \PWM_AUDIO:PWMUDB:runmode_enable\/q Net_1678/main_0 3.240
macrocell120 U(1,1) 1 Net_1678 HOLD 0.000
Clock Skew 0.000
\PWM_AUDIO:PWMUDB:runmode_enable\/q Net_1679/main_0 4.490
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell115 U(1,1) 1 \PWM_AUDIO:PWMUDB:runmode_enable\ \PWM_AUDIO:PWMUDB:runmode_enable\/clock_0 \PWM_AUDIO:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_AUDIO:PWMUDB:runmode_enable\ \PWM_AUDIO:PWMUDB:runmode_enable\/q Net_1679/main_0 3.240
macrocell121 U(1,1) 1 Net_1679 HOLD 0.000
Clock Skew 0.000
\PWM_AUDIO:PWMUDB:runmode_enable\/q \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 4.527
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell115 U(1,1) 1 \PWM_AUDIO:PWMUDB:runmode_enable\ \PWM_AUDIO:PWMUDB:runmode_enable\/clock_0 \PWM_AUDIO:PWMUDB:runmode_enable\/q 1.250
Route 1 \PWM_AUDIO:PWMUDB:runmode_enable\ \PWM_AUDIO:PWMUDB:runmode_enable\/q \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\/cs_addr_1 3.277
datapathcell13 U(1,1) 1 \PWM_AUDIO:PWMUDB:sP8:pwmdp:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\SPIM_ETH:BSPIM:BitCounter\/count_1 \SPIM_ETH:BSPIM:state_2\/main_6 3.227
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \SPIM_ETH:BSPIM:BitCounter\ \SPIM_ETH:BSPIM:BitCounter\/clock \SPIM_ETH:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM_ETH:BSPIM:count_1\ \SPIM_ETH:BSPIM:BitCounter\/count_1 \SPIM_ETH:BSPIM:state_2\/main_6 2.607
macrocell132 U(3,2) 1 \SPIM_ETH:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM_ETH:BSPIM:BitCounter\/count_2 \SPIM_ETH:BSPIM:state_2\/main_5 3.227
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \SPIM_ETH:BSPIM:BitCounter\ \SPIM_ETH:BSPIM:BitCounter\/clock \SPIM_ETH:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM_ETH:BSPIM:count_2\ \SPIM_ETH:BSPIM:BitCounter\/count_2 \SPIM_ETH:BSPIM:state_2\/main_5 2.607
macrocell132 U(3,2) 1 \SPIM_ETH:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM_ETH:BSPIM:BitCounter\/count_2 \SPIM_ETH:BSPIM:state_1\/main_5 3.227
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \SPIM_ETH:BSPIM:BitCounter\ \SPIM_ETH:BSPIM:BitCounter\/clock \SPIM_ETH:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM_ETH:BSPIM:count_2\ \SPIM_ETH:BSPIM:BitCounter\/count_2 \SPIM_ETH:BSPIM:state_1\/main_5 2.607
macrocell133 U(3,2) 1 \SPIM_ETH:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM_ETH:BSPIM:BitCounter\/count_1 \SPIM_ETH:BSPIM:state_1\/main_6 3.227
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \SPIM_ETH:BSPIM:BitCounter\ \SPIM_ETH:BSPIM:BitCounter\/clock \SPIM_ETH:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM_ETH:BSPIM:count_1\ \SPIM_ETH:BSPIM:BitCounter\/count_1 \SPIM_ETH:BSPIM:state_1\/main_6 2.607
macrocell133 U(3,2) 1 \SPIM_ETH:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM_ETH:BSPIM:BitCounter\/count_0 \SPIM_ETH:BSPIM:state_2\/main_7 3.228
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \SPIM_ETH:BSPIM:BitCounter\ \SPIM_ETH:BSPIM:BitCounter\/clock \SPIM_ETH:BSPIM:BitCounter\/count_0 0.620
Route 1 \SPIM_ETH:BSPIM:count_0\ \SPIM_ETH:BSPIM:BitCounter\/count_0 \SPIM_ETH:BSPIM:state_2\/main_7 2.608
macrocell132 U(3,2) 1 \SPIM_ETH:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
\SPIM_ETH:BSPIM:BitCounter\/count_0 \SPIM_ETH:BSPIM:state_1\/main_7 3.228
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \SPIM_ETH:BSPIM:BitCounter\ \SPIM_ETH:BSPIM:BitCounter\/clock \SPIM_ETH:BSPIM:BitCounter\/count_0 0.620
Route 1 \SPIM_ETH:BSPIM:count_0\ \SPIM_ETH:BSPIM:BitCounter\/count_0 \SPIM_ETH:BSPIM:state_1\/main_7 2.608
macrocell133 U(3,2) 1 \SPIM_ETH:BSPIM:state_1\ HOLD 0.000
Clock Skew 0.000
\SPIM_ETH:BSPIM:BitCounter\/count_2 Net_2277/main_7 3.235
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \SPIM_ETH:BSPIM:BitCounter\ \SPIM_ETH:BSPIM:BitCounter\/clock \SPIM_ETH:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM_ETH:BSPIM:count_2\ \SPIM_ETH:BSPIM:BitCounter\/count_2 Net_2277/main_7 2.615
macrocell131 U(3,2) 1 Net_2277 HOLD 0.000
Clock Skew 0.000
\SPIM_ETH:BSPIM:BitCounter\/count_1 Net_2277/main_8 3.237
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \SPIM_ETH:BSPIM:BitCounter\ \SPIM_ETH:BSPIM:BitCounter\/clock \SPIM_ETH:BSPIM:BitCounter\/count_1 0.620
Route 1 \SPIM_ETH:BSPIM:count_1\ \SPIM_ETH:BSPIM:BitCounter\/count_1 Net_2277/main_8 2.617
macrocell131 U(3,2) 1 Net_2277 HOLD 0.000
Clock Skew 0.000
\SPIM_ETH:BSPIM:BitCounter\/count_0 Net_2277/main_9 3.241
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(3,2) 1 \SPIM_ETH:BSPIM:BitCounter\ \SPIM_ETH:BSPIM:BitCounter\/clock \SPIM_ETH:BSPIM:BitCounter\/count_0 0.620
Route 1 \SPIM_ETH:BSPIM:count_0\ \SPIM_ETH:BSPIM:BitCounter\/count_0 Net_2277/main_9 2.621
macrocell131 U(3,2) 1 Net_2277 HOLD 0.000
Clock Skew 0.000
\SPIM_SD:BSPIM:BitCounter\/count_2 \SPIM_SD:BSPIM:state_2\/main_5 3.328
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(2,0) 1 \SPIM_SD:BSPIM:BitCounter\ \SPIM_SD:BSPIM:BitCounter\/clock \SPIM_SD:BSPIM:BitCounter\/count_2 0.620
Route 1 \SPIM_SD:BSPIM:count_2\ \SPIM_SD:BSPIM:BitCounter\/count_2 \SPIM_SD:BSPIM:state_2\/main_5 2.708
macrocell123 U(3,0) 1 \SPIM_SD:BSPIM:state_2\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Rx_1(0)/fb MODIN1_1/main_2 7.923
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P5[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.805
Route 1 Net_7 Rx_1(0)/fb MODIN1_1/main_2 5.118
macrocell63 U(0,0) 1 MODIN1_1 HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb MODIN1_0/main_2 7.923
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P5[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.805
Route 1 Net_7 Rx_1(0)/fb MODIN1_0/main_2 5.118
macrocell64 U(0,0) 1 MODIN1_0 HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_5 7.943
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P5[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.805
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_0\/main_5 5.138
macrocell57 U(0,0) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_5 7.943
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P5[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.805
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_status_3\/main_5 5.138
macrocell65 U(0,0) 1 \UART_1:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_5 8.786
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P5[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.805
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_state_2\/main_5 5.981
macrocell60 U(0,1) 1 \UART_1:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 8.786
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P5[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.805
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_last\/main_0 5.981
macrocell66 U(0,1) 1 \UART_1:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_1(0)/fb \UART_1:BUART:sRX:RxShifter:u0\/route_si 13.522
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell1 P5[4] 1 Rx_1(0) Rx_1(0)/in_clock Rx_1(0)/fb 2.805
Route 1 Net_7 Rx_1(0)/fb \UART_1:BUART:rx_postpoll\/main_0 5.118
macrocell7 U(0,0) 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/main_0 \UART_1:BUART:rx_postpoll\/q 3.350
Route 1 \UART_1:BUART:rx_postpoll\ \UART_1:BUART:rx_postpoll\/q \UART_1:BUART:sRX:RxShifter:u0\/route_si 2.249
datapathcell3 U(0,0) 1 \UART_1:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Rx_2(0)/fb MODIN5_1/main_2 6.688
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P2[4] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.035
Route 1 Net_1608 Rx_2(0)/fb MODIN5_1/main_2 4.653
macrocell79 U(0,4) 1 MODIN5_1 HOLD 0.000
Clock Skew 0.000
Rx_2(0)/fb MODIN5_0/main_2 6.688
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P2[4] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.035
Route 1 Net_1608 Rx_2(0)/fb MODIN5_0/main_2 4.653
macrocell80 U(0,4) 1 MODIN5_0 HOLD 0.000
Clock Skew 0.000
Rx_2(0)/fb \UART_2:BUART:rx_state_0\/main_5 7.598
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P2[4] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.035
Route 1 Net_1608 Rx_2(0)/fb \UART_2:BUART:rx_state_0\/main_5 5.563
macrocell73 U(0,3) 1 \UART_2:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_2(0)/fb \UART_2:BUART:rx_status_3\/main_5 7.598
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P2[4] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.035
Route 1 Net_1608 Rx_2(0)/fb \UART_2:BUART:rx_status_3\/main_5 5.563
macrocell81 U(0,3) 1 \UART_2:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_2(0)/fb \UART_2:BUART:rx_last\/main_0 7.615
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P2[4] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.035
Route 1 Net_1608 Rx_2(0)/fb \UART_2:BUART:rx_last\/main_0 5.580
macrocell82 U(0,5) 1 \UART_2:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_2(0)/fb \UART_2:BUART:rx_state_2\/main_5 8.521
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P2[4] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.035
Route 1 Net_1608 Rx_2(0)/fb \UART_2:BUART:rx_state_2\/main_5 6.486
macrocell76 U(0,2) 1 \UART_2:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_2(0)/fb \UART_2:BUART:sRX:RxShifter:u0\/route_si 12.347
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell3 P2[4] 1 Rx_2(0) Rx_2(0)/in_clock Rx_2(0)/fb 2.035
Route 1 Net_1608 Rx_2(0)/fb \UART_2:BUART:rx_postpoll\/main_0 4.653
macrocell17 U(0,4) 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/main_0 \UART_2:BUART:rx_postpoll\/q 3.350
Route 1 \UART_2:BUART:rx_postpoll\ \UART_2:BUART:rx_postpoll\/q \UART_2:BUART:sRX:RxShifter:u0\/route_si 2.309
datapathcell6 U(0,4) 1 \UART_2:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Rx_3(0)/fb \UART_3:BUART:rx_state_0\/main_5 7.574
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P2[2] 1 Rx_3(0) Rx_3(0)/in_clock Rx_3(0)/fb 2.503
Route 1 Net_1619 Rx_3(0)/fb \UART_3:BUART:rx_state_0\/main_5 5.071
macrocell89 U(0,4) 1 \UART_3:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_3(0)/fb \UART_3:BUART:rx_status_3\/main_5 7.574
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P2[2] 1 Rx_3(0) Rx_3(0)/in_clock Rx_3(0)/fb 2.503
Route 1 Net_1619 Rx_3(0)/fb \UART_3:BUART:rx_status_3\/main_5 5.071
macrocell97 U(0,4) 1 \UART_3:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_3(0)/fb \UART_3:BUART:rx_last\/main_0 7.574
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P2[2] 1 Rx_3(0) Rx_3(0)/in_clock Rx_3(0)/fb 2.503
Route 1 Net_1619 Rx_3(0)/fb \UART_3:BUART:rx_last\/main_0 5.071
macrocell98 U(0,4) 1 \UART_3:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_3(0)/fb MODIN9_1/main_2 8.312
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P2[2] 1 Rx_3(0) Rx_3(0)/in_clock Rx_3(0)/fb 2.503
Route 1 Net_1619 Rx_3(0)/fb MODIN9_1/main_2 5.809
macrocell95 U(0,3) 1 MODIN9_1 HOLD 0.000
Clock Skew 0.000
Rx_3(0)/fb MODIN9_0/main_2 8.312
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P2[2] 1 Rx_3(0) Rx_3(0)/in_clock Rx_3(0)/fb 2.503
Route 1 Net_1619 Rx_3(0)/fb MODIN9_0/main_2 5.809
macrocell96 U(0,3) 1 MODIN9_0 HOLD 0.000
Clock Skew 0.000
Rx_3(0)/fb \UART_3:BUART:rx_state_2\/main_5 9.239
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P2[2] 1 Rx_3(0) Rx_3(0)/in_clock Rx_3(0)/fb 2.503
Route 1 Net_1619 Rx_3(0)/fb \UART_3:BUART:rx_state_2\/main_5 6.736
macrocell92 U(0,2) 1 \UART_3:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_3(0)/fb \UART_3:BUART:sRX:RxShifter:u0\/route_si 14.562
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell5 P2[2] 1 Rx_3(0) Rx_3(0)/in_clock Rx_3(0)/fb 2.503
Route 1 Net_1619 Rx_3(0)/fb \UART_3:BUART:rx_postpoll\/main_0 5.809
macrocell27 U(0,3) 1 \UART_3:BUART:rx_postpoll\ \UART_3:BUART:rx_postpoll\/main_0 \UART_3:BUART:rx_postpoll\/q 3.350
Route 1 \UART_3:BUART:rx_postpoll\ \UART_3:BUART:rx_postpoll\/q \UART_3:BUART:sRX:RxShifter:u0\/route_si 2.900
datapathcell9 U(0,2) 1 \UART_3:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
Rx_4(0)/fb \UART_4:BUART:pollcount_1\/main_3 7.238
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P2[0] 1 Rx_4(0) Rx_4(0)/in_clock Rx_4(0)/fb 2.187
Route 1 Net_1630 Rx_4(0)/fb \UART_4:BUART:pollcount_1\/main_3 5.051
macrocell111 U(1,4) 1 \UART_4:BUART:pollcount_1\ HOLD 0.000
Clock Skew 0.000
Rx_4(0)/fb \UART_4:BUART:pollcount_0\/main_2 7.238
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P2[0] 1 Rx_4(0) Rx_4(0)/in_clock Rx_4(0)/fb 2.187
Route 1 Net_1630 Rx_4(0)/fb \UART_4:BUART:pollcount_0\/main_2 5.051
macrocell112 U(1,4) 1 \UART_4:BUART:pollcount_0\ HOLD 0.000
Clock Skew 0.000
Rx_4(0)/fb \UART_4:BUART:rx_last\/main_0 7.991
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P2[0] 1 Rx_4(0) Rx_4(0)/in_clock Rx_4(0)/fb 2.187
Route 1 Net_1630 Rx_4(0)/fb \UART_4:BUART:rx_last\/main_0 5.804
macrocell114 U(1,3) 1 \UART_4:BUART:rx_last\ HOLD 0.000
Clock Skew 0.000
Rx_4(0)/fb \UART_4:BUART:rx_state_0\/main_9 8.306
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P2[0] 1 Rx_4(0) Rx_4(0)/in_clock Rx_4(0)/fb 2.187
Route 1 Net_1630 Rx_4(0)/fb \UART_4:BUART:rx_state_0\/main_9 6.119
macrocell105 U(1,5) 1 \UART_4:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
Rx_4(0)/fb \UART_4:BUART:rx_status_3\/main_6 8.306
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P2[0] 1 Rx_4(0) Rx_4(0)/in_clock Rx_4(0)/fb 2.187
Route 1 Net_1630 Rx_4(0)/fb \UART_4:BUART:rx_status_3\/main_6 6.119
macrocell113 U(1,5) 1 \UART_4:BUART:rx_status_3\ HOLD 0.000
Clock Skew 0.000
Rx_4(0)/fb \UART_4:BUART:rx_state_2\/main_8 8.322
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P2[0] 1 Rx_4(0) Rx_4(0)/in_clock Rx_4(0)/fb 2.187
Route 1 Net_1630 Rx_4(0)/fb \UART_4:BUART:rx_state_2\/main_8 6.135
macrocell108 U(1,5) 1 \UART_4:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
Rx_4(0)/fb \UART_4:BUART:sRX:RxShifter:u0\/route_si 12.880
Type Location Fanout Instance/Net Source Dest Delay (ns)
iocell7 P2[0] 1 Rx_4(0) Rx_4(0)/in_clock Rx_4(0)/fb 2.187
Route 1 Net_1630 Rx_4(0)/fb \UART_4:BUART:rx_postpoll\/main_1 5.051
macrocell37 U(1,4) 1 \UART_4:BUART:rx_postpoll\ \UART_4:BUART:rx_postpoll\/main_1 \UART_4:BUART:rx_postpoll\/q 3.350
Route 1 \UART_4:BUART:rx_postpoll\ \UART_4:BUART:rx_postpoll\/q \UART_4:BUART:sRX:RxShifter:u0\/route_si 2.292
datapathcell12 U(1,4) 1 \UART_4:BUART:sRX:RxShifter:u0\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:rx_bitclk_enable\/main_1 2.868
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART_1:BUART:rx_count_1\ \UART_1:BUART:sRX:RxBitCounter\/count_1 \UART_1:BUART:rx_bitclk_enable\/main_1 2.248
macrocell61 U(0,0) 1 \UART_1:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_1 MODIN1_1/main_1 2.868
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART_1:BUART:rx_count_1\ \UART_1:BUART:sRX:RxBitCounter\/count_1 MODIN1_1/main_1 2.248
macrocell63 U(0,0) 1 MODIN1_1 HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_1 MODIN1_0/main_1 2.868
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART_1:BUART:rx_count_1\ \UART_1:BUART:sRX:RxBitCounter\/count_1 MODIN1_0/main_1 2.248
macrocell64 U(0,0) 1 MODIN1_0 HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_0\/main_9 2.870
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 MODIN4_5 \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_state_0\/main_9 2.250
macrocell57 U(0,0) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_load_fifo\/main_6 2.870
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 MODIN4_5 \UART_1:BUART:sRX:RxBitCounter\/count_5 \UART_1:BUART:rx_load_fifo\/main_6 2.250
macrocell58 U(0,0) 1 \UART_1:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_state_0\/main_8 2.871
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 MODIN4_6 \UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_state_0\/main_8 2.251
macrocell57 U(0,0) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_load_fifo\/main_5 2.871
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 MODIN4_6 \UART_1:BUART:sRX:RxBitCounter\/count_6 \UART_1:BUART:rx_load_fifo\/main_5 2.251
macrocell58 U(0,0) 1 \UART_1:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_state_0\/main_10 2.872
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 MODIN4_4 \UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_state_0\/main_10 2.252
macrocell57 U(0,0) 1 \UART_1:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_load_fifo\/main_7 2.872
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 MODIN4_4 \UART_1:BUART:sRX:RxBitCounter\/count_4 \UART_1:BUART:rx_load_fifo\/main_7 2.252
macrocell58 U(0,0) 1 \UART_1:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:rx_bitclk_enable\/main_0 2.873
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,0) 1 \UART_1:BUART:sRX:RxBitCounter\ \UART_1:BUART:sRX:RxBitCounter\/clock \UART_1:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART_1:BUART:rx_count_2\ \UART_1:BUART:sRX:RxBitCounter\/count_2 \UART_1:BUART:rx_bitclk_enable\/main_0 2.253
macrocell61 U(0,0) 1 \UART_1:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_2:BUART:sRX:RxBitCounter\/count_6 \UART_2:BUART:rx_state_0\/main_8 2.923
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \UART_2:BUART:sRX:RxBitCounter\ \UART_2:BUART:sRX:RxBitCounter\/clock \UART_2:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 MODIN8_6 \UART_2:BUART:sRX:RxBitCounter\/count_6 \UART_2:BUART:rx_state_0\/main_8 2.303
macrocell73 U(0,3) 1 \UART_2:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:sRX:RxBitCounter\/count_6 \UART_2:BUART:rx_load_fifo\/main_5 2.923
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \UART_2:BUART:sRX:RxBitCounter\ \UART_2:BUART:sRX:RxBitCounter\/clock \UART_2:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 MODIN8_6 \UART_2:BUART:sRX:RxBitCounter\/count_6 \UART_2:BUART:rx_load_fifo\/main_5 2.303
macrocell74 U(0,3) 1 \UART_2:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:sRX:RxBitCounter\/count_5 \UART_2:BUART:rx_state_0\/main_9 2.925
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \UART_2:BUART:sRX:RxBitCounter\ \UART_2:BUART:sRX:RxBitCounter\/clock \UART_2:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 MODIN8_5 \UART_2:BUART:sRX:RxBitCounter\/count_5 \UART_2:BUART:rx_state_0\/main_9 2.305
macrocell73 U(0,3) 1 \UART_2:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:sRX:RxBitCounter\/count_5 \UART_2:BUART:rx_load_fifo\/main_6 2.925
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \UART_2:BUART:sRX:RxBitCounter\ \UART_2:BUART:sRX:RxBitCounter\/clock \UART_2:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 MODIN8_5 \UART_2:BUART:sRX:RxBitCounter\/count_5 \UART_2:BUART:rx_load_fifo\/main_6 2.305
macrocell74 U(0,3) 1 \UART_2:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:sRX:RxBitCounter\/count_4 \UART_2:BUART:rx_state_0\/main_10 2.942
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \UART_2:BUART:sRX:RxBitCounter\ \UART_2:BUART:sRX:RxBitCounter\/clock \UART_2:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 MODIN8_4 \UART_2:BUART:sRX:RxBitCounter\/count_4 \UART_2:BUART:rx_state_0\/main_10 2.322
macrocell73 U(0,3) 1 \UART_2:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:sRX:RxBitCounter\/count_4 \UART_2:BUART:rx_load_fifo\/main_7 2.942
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \UART_2:BUART:sRX:RxBitCounter\ \UART_2:BUART:sRX:RxBitCounter\/clock \UART_2:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 MODIN8_4 \UART_2:BUART:sRX:RxBitCounter\/count_4 \UART_2:BUART:rx_load_fifo\/main_7 2.322
macrocell74 U(0,3) 1 \UART_2:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:sRX:RxBitCounter\/count_2 \UART_2:BUART:rx_bitclk_enable\/main_0 3.498
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \UART_2:BUART:sRX:RxBitCounter\ \UART_2:BUART:sRX:RxBitCounter\/clock \UART_2:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART_2:BUART:rx_count_2\ \UART_2:BUART:sRX:RxBitCounter\/count_2 \UART_2:BUART:rx_bitclk_enable\/main_0 2.878
macrocell77 U(0,4) 1 \UART_2:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:sRX:RxBitCounter\/count_2 MODIN5_1/main_0 3.498
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \UART_2:BUART:sRX:RxBitCounter\ \UART_2:BUART:sRX:RxBitCounter\/clock \UART_2:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART_2:BUART:rx_count_2\ \UART_2:BUART:sRX:RxBitCounter\/count_2 MODIN5_1/main_0 2.878
macrocell79 U(0,4) 1 MODIN5_1 HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:sRX:RxBitCounter\/count_2 MODIN5_0/main_0 3.498
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \UART_2:BUART:sRX:RxBitCounter\ \UART_2:BUART:sRX:RxBitCounter\/clock \UART_2:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART_2:BUART:rx_count_2\ \UART_2:BUART:sRX:RxBitCounter\/count_2 MODIN5_0/main_0 2.878
macrocell80 U(0,4) 1 MODIN5_0 HOLD 0.000
Clock Skew 0.000
\UART_2:BUART:sRX:RxBitCounter\/count_1 \UART_2:BUART:rx_bitclk_enable\/main_1 3.511
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,3) 1 \UART_2:BUART:sRX:RxBitCounter\ \UART_2:BUART:sRX:RxBitCounter\/clock \UART_2:BUART:sRX:RxBitCounter\/count_1 0.620
Route 1 \UART_2:BUART:rx_count_1\ \UART_2:BUART:sRX:RxBitCounter\/count_1 \UART_2:BUART:rx_bitclk_enable\/main_1 2.891
macrocell77 U(0,4) 1 \UART_2:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_3:BUART:sRX:RxBitCounter\/count_6 \UART_3:BUART:rx_load_fifo\/main_5 2.936
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,2) 1 \UART_3:BUART:sRX:RxBitCounter\ \UART_3:BUART:sRX:RxBitCounter\/clock \UART_3:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 MODIN12_6 \UART_3:BUART:sRX:RxBitCounter\/count_6 \UART_3:BUART:rx_load_fifo\/main_5 2.316
macrocell90 U(0,2) 1 \UART_3:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_3:BUART:sRX:RxBitCounter\/count_6 \UART_3:BUART:rx_state_2\/main_7 2.936
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,2) 1 \UART_3:BUART:sRX:RxBitCounter\ \UART_3:BUART:sRX:RxBitCounter\/clock \UART_3:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 MODIN12_6 \UART_3:BUART:sRX:RxBitCounter\/count_6 \UART_3:BUART:rx_state_2\/main_7 2.316
macrocell92 U(0,2) 1 \UART_3:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_3:BUART:sRX:RxBitCounter\/count_5 \UART_3:BUART:rx_load_fifo\/main_6 2.937
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,2) 1 \UART_3:BUART:sRX:RxBitCounter\ \UART_3:BUART:sRX:RxBitCounter\/clock \UART_3:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 MODIN12_5 \UART_3:BUART:sRX:RxBitCounter\/count_5 \UART_3:BUART:rx_load_fifo\/main_6 2.317
macrocell90 U(0,2) 1 \UART_3:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_3:BUART:sRX:RxBitCounter\/count_5 \UART_3:BUART:rx_state_2\/main_8 2.937
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,2) 1 \UART_3:BUART:sRX:RxBitCounter\ \UART_3:BUART:sRX:RxBitCounter\/clock \UART_3:BUART:sRX:RxBitCounter\/count_5 0.620
Route 1 MODIN12_5 \UART_3:BUART:sRX:RxBitCounter\/count_5 \UART_3:BUART:rx_state_2\/main_8 2.317
macrocell92 U(0,2) 1 \UART_3:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_3:BUART:sRX:RxBitCounter\/count_4 \UART_3:BUART:rx_load_fifo\/main_7 2.939
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,2) 1 \UART_3:BUART:sRX:RxBitCounter\ \UART_3:BUART:sRX:RxBitCounter\/clock \UART_3:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 MODIN12_4 \UART_3:BUART:sRX:RxBitCounter\/count_4 \UART_3:BUART:rx_load_fifo\/main_7 2.319
macrocell90 U(0,2) 1 \UART_3:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_3:BUART:sRX:RxBitCounter\/count_4 \UART_3:BUART:rx_state_2\/main_9 2.939
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,2) 1 \UART_3:BUART:sRX:RxBitCounter\ \UART_3:BUART:sRX:RxBitCounter\/clock \UART_3:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 MODIN12_4 \UART_3:BUART:sRX:RxBitCounter\/count_4 \UART_3:BUART:rx_state_2\/main_9 2.319
macrocell92 U(0,2) 1 \UART_3:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_3:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_3:BUART:tx_bitclk\/main_0 3.083
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell8 U(3,4) 1 \UART_3:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_3:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_3:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb 0.780
Route 1 \UART_3:BUART:tx_bitclk_dp\ \UART_3:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_3:BUART:tx_bitclk\/main_0 2.303
macrocell87 U(3,4) 1 \UART_3:BUART:tx_bitclk\ HOLD 0.000
Clock Skew 0.000
\UART_3:BUART:sRX:RxBitCounter\/count_0 \UART_3:BUART:rx_bitclk_enable\/main_2 3.493
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,2) 1 \UART_3:BUART:sRX:RxBitCounter\ \UART_3:BUART:sRX:RxBitCounter\/clock \UART_3:BUART:sRX:RxBitCounter\/count_0 0.620
Route 1 \UART_3:BUART:rx_count_0\ \UART_3:BUART:sRX:RxBitCounter\/count_0 \UART_3:BUART:rx_bitclk_enable\/main_2 2.873
macrocell93 U(0,3) 1 \UART_3:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART_3:BUART:sRX:RxBitCounter\/count_2 \UART_3:BUART:rx_bitclk_enable\/main_0 3.513
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,2) 1 \UART_3:BUART:sRX:RxBitCounter\ \UART_3:BUART:sRX:RxBitCounter\/clock \UART_3:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART_3:BUART:rx_count_2\ \UART_3:BUART:sRX:RxBitCounter\/count_2 \UART_3:BUART:rx_bitclk_enable\/main_0 2.893
macrocell93 U(0,3) 1 \UART_3:BUART:rx_bitclk_enable\ HOLD 0.000
Clock Skew 0.000
\UART_3:BUART:sRX:RxBitCounter\/count_2 MODIN9_1/main_0 3.513
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(0,2) 1 \UART_3:BUART:sRX:RxBitCounter\ \UART_3:BUART:sRX:RxBitCounter\/clock \UART_3:BUART:sRX:RxBitCounter\/count_2 0.620
Route 1 \UART_3:BUART:rx_count_2\ \UART_3:BUART:sRX:RxBitCounter\/count_2 MODIN9_1/main_0 2.893
macrocell95 U(0,3) 1 MODIN9_1 HOLD 0.000
Clock Skew 0.000
Source Destination Slack (ns) Violation
\UART_4:BUART:rx_status_3\/q \UART_4:BUART:sRX:RxSts\/status_3 2.896
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell113 U(1,5) 1 \UART_4:BUART:rx_status_3\ \UART_4:BUART:rx_status_3\/clock_0 \UART_4:BUART:rx_status_3\/q 1.250
Route 1 \UART_4:BUART:rx_status_3\ \UART_4:BUART:rx_status_3\/q \UART_4:BUART:sRX:RxSts\/status_3 3.646
statusicell8 U(1,3) 1 \UART_4:BUART:sRX:RxSts\ HOLD -2.000
Clock Skew 0.000
\UART_4:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_4:BUART:tx_bitclk\/main_0 3.084
Type Location Fanout Instance/Net Source Dest Delay (ns)
datapathcell11 U(2,3) 1 \UART_4:BUART:sTX:sCLOCK:TxBitClkGen\ \UART_4:BUART:sTX:sCLOCK:TxBitClkGen\/clock \UART_4:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb 0.780
Route 1 \UART_4:BUART:tx_bitclk_dp\ \UART_4:BUART:sTX:sCLOCK:TxBitClkGen\/cl0_comb \UART_4:BUART:tx_bitclk\/main_0 2.304
macrocell103 U(2,3) 1 \UART_4:BUART:tx_bitclk\ HOLD 0.000
Clock Skew 0.000
\UART_4:BUART:sRX:RxBitCounter\/count_6 \UART_4:BUART:rx_state_2\/main_5 3.411
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \UART_4:BUART:sRX:RxBitCounter\ \UART_4:BUART:sRX:RxBitCounter\/clock \UART_4:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART_4:BUART:rx_count_6\ \UART_4:BUART:sRX:RxBitCounter\/count_6 \UART_4:BUART:rx_state_2\/main_5 2.791
macrocell108 U(1,5) 1 \UART_4:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_4:BUART:sRX:RxBitCounter\/count_6 \UART_4:BUART:rx_state_0\/main_5 3.413
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \UART_4:BUART:sRX:RxBitCounter\ \UART_4:BUART:sRX:RxBitCounter\/clock \UART_4:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART_4:BUART:rx_count_6\ \UART_4:BUART:sRX:RxBitCounter\/count_6 \UART_4:BUART:rx_state_0\/main_5 2.793
macrocell105 U(1,5) 1 \UART_4:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_4:BUART:sRX:RxBitCounter\/count_6 \UART_4:BUART:rx_load_fifo\/main_5 3.413
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \UART_4:BUART:sRX:RxBitCounter\ \UART_4:BUART:sRX:RxBitCounter\/clock \UART_4:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART_4:BUART:rx_count_6\ \UART_4:BUART:sRX:RxBitCounter\/count_6 \UART_4:BUART:rx_load_fifo\/main_5 2.793
macrocell106 U(1,5) 1 \UART_4:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_4:BUART:sRX:RxBitCounter\/count_6 \UART_4:BUART:rx_state_3\/main_5 3.413
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \UART_4:BUART:sRX:RxBitCounter\ \UART_4:BUART:sRX:RxBitCounter\/clock \UART_4:BUART:sRX:RxBitCounter\/count_6 0.620
Route 1 \UART_4:BUART:rx_count_6\ \UART_4:BUART:sRX:RxBitCounter\/count_6 \UART_4:BUART:rx_state_3\/main_5 2.793
macrocell107 U(1,5) 1 \UART_4:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
\UART_4:BUART:sRX:RxBitCounter\/count_4 \UART_4:BUART:rx_state_2\/main_7 3.423
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \UART_4:BUART:sRX:RxBitCounter\ \UART_4:BUART:sRX:RxBitCounter\/clock \UART_4:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART_4:BUART:rx_count_4\ \UART_4:BUART:sRX:RxBitCounter\/count_4 \UART_4:BUART:rx_state_2\/main_7 2.803
macrocell108 U(1,5) 1 \UART_4:BUART:rx_state_2\ HOLD 0.000
Clock Skew 0.000
\UART_4:BUART:sRX:RxBitCounter\/count_4 \UART_4:BUART:rx_state_0\/main_7 3.436
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \UART_4:BUART:sRX:RxBitCounter\ \UART_4:BUART:sRX:RxBitCounter\/clock \UART_4:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART_4:BUART:rx_count_4\ \UART_4:BUART:sRX:RxBitCounter\/count_4 \UART_4:BUART:rx_state_0\/main_7 2.816
macrocell105 U(1,5) 1 \UART_4:BUART:rx_state_0\ HOLD 0.000
Clock Skew 0.000
\UART_4:BUART:sRX:RxBitCounter\/count_4 \UART_4:BUART:rx_load_fifo\/main_7 3.436
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \UART_4:BUART:sRX:RxBitCounter\ \UART_4:BUART:sRX:RxBitCounter\/clock \UART_4:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART_4:BUART:rx_count_4\ \UART_4:BUART:sRX:RxBitCounter\/count_4 \UART_4:BUART:rx_load_fifo\/main_7 2.816
macrocell106 U(1,5) 1 \UART_4:BUART:rx_load_fifo\ HOLD 0.000
Clock Skew 0.000
\UART_4:BUART:sRX:RxBitCounter\/count_4 \UART_4:BUART:rx_state_3\/main_7 3.436
Type Location Fanout Instance/Net Source Dest Delay (ns)
count7cell U(1,5) 1 \UART_4:BUART:sRX:RxBitCounter\ \UART_4:BUART:sRX:RxBitCounter\/clock \UART_4:BUART:sRX:RxBitCounter\/count_4 0.620
Route 1 \UART_4:BUART:rx_count_4\ \UART_4:BUART:sRX:RxBitCounter\/count_4 \UART_4:BUART:rx_state_3\/main_7 2.816
macrocell107 U(1,5) 1 \UART_4:BUART:rx_state_3\ HOLD 0.000
Clock Skew 0.000
+ Input To Clock Section
+ Clock_3
Source Destination Delay (ns)
SD_MISO(0)_PAD \SPIM_SD:BSPIM:sR8:Dp:u0\/route_si 15.798
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 SD_MISO(0)_PAD SD_MISO(0)_PAD SD_MISO(0)/pad_in 0.000
iocell15 P3[0] 1 SD_MISO(0) SD_MISO(0)/pad_in SD_MISO(0)/fb 6.324
Route 1 Net_1767 SD_MISO(0)/fb \SPIM_SD:BSPIM:sR8:Dp:u0\/route_si 5.974
datapathcell14 U(3,1) 1 \SPIM_SD:BSPIM:sR8:Dp:u0\ SETUP 3.500
Clock Clock path delay 0.000
ETH_MISO(0)_PAD \SPIM_ETH:BSPIM:sR8:Dp:u0\/route_si 15.379
Type Location Fanout Instance/Net Source Dest Delay (ns)
Route 1 ETH_MISO(0)_PAD ETH_MISO(0)_PAD ETH_MISO(0)/pad_in 0.000
iocell19 P3[4] 1 ETH_MISO(0) ETH_MISO(0)/pad_in ETH_MISO(0)/fb 6.038
Route 1 Net_2280 ETH_MISO(0)/fb \SPIM_ETH:BSPIM:sR8:Dp:u0\/route_si 5.841
datapathcell15 U(3,2) 1 \SPIM_ETH:BSPIM:sR8:Dp:u0\ SETUP 3.500
Clock Clock path delay 0.000
+ Clock To Output Section
+ Clock_2
Source Destination Delay (ns)
Net_1678/q AUDIO_L(0)_PAD 23.266
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell120 U(1,1) 1 Net_1678 Net_1678/clock_0 Net_1678/q 1.250
Route 1 Net_1678 Net_1678/q AUDIO_L(0)/pin_input 6.602
iocell13 P5[6] 1 AUDIO_L(0) AUDIO_L(0)/pin_input AUDIO_L(0)/pad_out 15.414
Route 1 AUDIO_L(0)_PAD AUDIO_L(0)/pad_out AUDIO_L(0)_PAD 0.000
Clock Clock path delay 0.000
Net_1679/q AUDIO_R(0)_PAD 22.541
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell121 U(1,1) 1 Net_1679 Net_1679/clock_0 Net_1679/q 1.250
Route 1 Net_1679 Net_1679/q AUDIO_R(0)/pin_input 6.507
iocell14 P5[7] 1 AUDIO_R(0) AUDIO_R(0)/pin_input AUDIO_R(0)/pad_out 14.784
Route 1 AUDIO_R(0)_PAD AUDIO_R(0)/pad_out AUDIO_R(0)_PAD 0.000
Clock Clock path delay 0.000
+ Clock_3
Source Destination Delay (ns)
Net_2278/q ETH_SCLK(0)_PAD 24.180
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell139 U(2,3) 1 Net_2278 Net_2278/clock_0 Net_2278/q 1.250
Route 1 Net_2278 Net_2278/q ETH_SCLK(0)/pin_input 7.592
iocell21 P3[5] 1 ETH_SCLK(0) ETH_SCLK(0)/pin_input ETH_SCLK(0)/pad_out 15.338
Route 1 ETH_SCLK(0)_PAD ETH_SCLK(0)/pad_out ETH_SCLK(0)_PAD 0.000
Clock Clock path delay 0.000
Net_1765/q SD_SCLK(0)_PAD 23.666
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell130 U(1,0) 1 Net_1765 Net_1765/clock_0 Net_1765/q 1.250
Route 1 Net_1765 Net_1765/q SD_SCLK(0)/pin_input 7.437
iocell17 P3[1] 1 SD_SCLK(0) SD_SCLK(0)/pin_input SD_SCLK(0)/pad_out 14.979
Route 1 SD_SCLK(0)_PAD SD_SCLK(0)/pad_out SD_SCLK(0)_PAD 0.000
Clock Clock path delay 0.000
Net_2279/q ETH_SS(0)_PAD 23.381
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell135 U(2,3) 1 Net_2279 Net_2279/clock_0 Net_2279/q 1.250
Route 1 Net_2279 Net_2279/q ETH_SS(0)/pin_input 6.970
iocell22 P3[7] 1 ETH_SS(0) ETH_SS(0)/pin_input ETH_SS(0)/pad_out 15.161
Route 1 ETH_SS(0)_PAD ETH_SS(0)/pad_out ETH_SS(0)_PAD 0.000
Clock Clock path delay 0.000
Net_1766/q SD_SS(0)_PAD 23.239
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell126 U(1,0) 1 Net_1766 Net_1766/clock_0 Net_1766/q 1.250
Route 1 Net_1766 Net_1766/q SD_SS(0)/pin_input 7.398
iocell18 P3[3] 1 SD_SS(0) SD_SS(0)/pin_input SD_SS(0)/pad_out 14.591
Route 1 SD_SS(0)_PAD SD_SS(0)/pad_out SD_SS(0)_PAD 0.000
Clock Clock path delay 0.000
Net_2277/q ETH_MOSI(0)_PAD 22.044
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell131 U(3,2) 1 Net_2277 Net_2277/clock_0 Net_2277/q 1.250
Route 1 Net_2277 Net_2277/q ETH_MOSI(0)/pin_input 6.203
iocell20 P3[6] 1 ETH_MOSI(0) ETH_MOSI(0)/pin_input ETH_MOSI(0)/pad_out 14.591
Route 1 ETH_MOSI(0)_PAD ETH_MOSI(0)/pad_out ETH_MOSI(0)_PAD 0.000
Clock Clock path delay 0.000
Net_1764/q SD_MOSI(0)_PAD 21.925
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell122 U(3,0) 1 Net_1764 Net_1764/clock_0 Net_1764/q 1.250
Route 1 Net_1764 Net_1764/q SD_MOSI(0)/pin_input 5.680
iocell16 P3[2] 1 SD_MOSI(0) SD_MOSI(0)/pin_input SD_MOSI(0)/pad_out 14.995
Route 1 SD_MOSI(0)_PAD SD_MOSI(0)/pad_out SD_MOSI(0)_PAD 0.000
Clock Clock path delay 0.000
+ CyBUS_CLK(fixed-function)
Source Destination Delay (ns)
\Timer_CAM:TimerHW\/tc CAM_XK(0)_PAD 23.794
Type Location Fanout Instance/Net Source Dest Delay (ns)
timercell F(Timer,1) 1 \Timer_CAM:TimerHW\ \Timer_CAM:TimerHW\/clock \Timer_CAM:TimerHW\/tc 1.000
Route 1 Net_3043 \Timer_CAM:TimerHW\/tc CAM_XK(0)/pin_input 7.920
iocell33 P2[7] 1 CAM_XK(0) CAM_XK(0)/pin_input CAM_XK(0)/pad_out 14.874
Route 1 CAM_XK(0)_PAD CAM_XK(0)/pad_out CAM_XK(0)_PAD 0.000
Clock Clock path delay 0.000
\I2C_1:I2C_FF\/scl_out SCL_1(0)_PAD:out 19.045
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2C_1:I2C_FF\ \I2C_1:I2C_FF\/clock \I2C_1:I2C_FF\/scl_out 1.000
Route 1 \I2C_1:Net_643_0\ \I2C_1:I2C_FF\/scl_out SCL_1(0)/pin_input 2.664
iocell24 P1[7] 1 SCL_1(0) SCL_1(0)/pin_input SCL_1(0)/pad_out 15.381
Route 1 SCL_1(0)_PAD SCL_1(0)/pad_out SCL_1(0)_PAD:out 0.000
Clock Clock path delay 0.000
\I2C_1:I2C_FF\/sda_out SDA_1(0)_PAD:out 18.736
Type Location Fanout Instance/Net Source Dest Delay (ns)
i2ccell F(I2C,0) 1 \I2C_1:I2C_FF\ \I2C_1:I2C_FF\/clock \I2C_1:I2C_FF\/sda_out 1.000
Route 1 \I2C_1:sda_x_wire\ \I2C_1:I2C_FF\/sda_out SDA_1(0)/pin_input 2.665
iocell23 P1[6] 1 SDA_1(0) SDA_1(0)/pin_input SDA_1(0)/pad_out 15.071
Route 1 SDA_1(0)_PAD SDA_1(0)/pad_out SDA_1(0)_PAD:out 0.000
Clock Clock path delay 0.000
+ UART_1_IntClock
Source Destination Delay (ns)
\UART_1:BUART:txn\/q Tx_1(0)_PAD 28.249
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell51 U(2,0) 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/clock_0 \UART_1:BUART:txn\/q 1.250
Route 1 \UART_1:BUART:txn\ \UART_1:BUART:txn\/q Net_2/main_0 2.255
macrocell1 U(2,0) 1 Net_2 Net_2/main_0 Net_2/q 3.350
Route 1 Net_2 Net_2/q Tx_1(0)/pin_input 7.004
iocell2 P5[5] 1 Tx_1(0) Tx_1(0)/pin_input Tx_1(0)/pad_out 14.390
Route 1 Tx_1(0)_PAD Tx_1(0)/pad_out Tx_1(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_2_IntClock
Source Destination Delay (ns)
\UART_2:BUART:txn\/q Tx_2(0)_PAD 30.055
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell67 U(2,5) 1 \UART_2:BUART:txn\ \UART_2:BUART:txn\/clock_0 \UART_2:BUART:txn\/q 1.250
Route 1 \UART_2:BUART:txn\ \UART_2:BUART:txn\/q Net_1603/main_0 2.288
macrocell11 U(2,5) 1 Net_1603 Net_1603/main_0 Net_1603/q 3.350
Route 1 Net_1603 Net_1603/q Tx_2(0)/pin_input 7.514
iocell4 P2[5] 1 Tx_2(0) Tx_2(0)/pin_input Tx_2(0)/pad_out 15.653
Route 1 Tx_2(0)_PAD Tx_2(0)/pad_out Tx_2(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_3_IntClock
Source Destination Delay (ns)
\UART_3:BUART:txn\/q Tx_3(0)_PAD 30.158
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell83 U(3,3) 1 \UART_3:BUART:txn\ \UART_3:BUART:txn\/clock_0 \UART_3:BUART:txn\/q 1.250
Route 1 \UART_3:BUART:txn\ \UART_3:BUART:txn\/q Net_1614/main_0 2.584
macrocell21 U(2,3) 1 Net_1614 Net_1614/main_0 Net_1614/q 3.350
Route 1 Net_1614 Net_1614/q Tx_3(0)/pin_input 7.537
iocell6 P2[3] 1 Tx_3(0) Tx_3(0)/pin_input Tx_3(0)/pad_out 15.437
Route 1 Tx_3(0)_PAD Tx_3(0)/pad_out Tx_3(0)_PAD 0.000
Clock Clock path delay 0.000
+ UART_4_IntClock
Source Destination Delay (ns)
\UART_4:BUART:txn\/q Tx_4(0)_PAD 29.998
Type Location Fanout Instance/Net Source Dest Delay (ns)
macrocell99 U(2,4) 1 \UART_4:BUART:txn\ \UART_4:BUART:txn\/clock_0 \UART_4:BUART:txn\/q 1.250
Route 1 \UART_4:BUART:txn\ \UART_4:BUART:txn\/q Net_1625/main_0 2.308
macrocell31 U(2,4) 1 Net_1625 Net_1625/main_0 Net_1625/q 3.350
Route 1 Net_1625 Net_1625/q Tx_4(0)/pin_input 7.199
iocell8 P2[1] 1 Tx_4(0) Tx_4(0)/pin_input Tx_4(0)/pad_out 15.891
Route 1 Tx_4(0)_PAD Tx_4(0)/pad_out Tx_4(0)_PAD 0.000
Clock Clock path delay 0.000